A global technology company is seeking a Staff Logic Design Engineer in Milpitas, CA. The candidate will architect and implement high-performance digital logic for protocol analysis on FPGA-based systems, requiring 7+ years of experience in digital logic design and strong proficiency in Verilog/SystemVerilog. This role offers a competitive salary range of $141,900.00-$189,200.00 and requires collaboration with cross-functional teams to deliver innovative solutions.
Qualifications
7+ years of experience in digital logic design for FPGA or ASIC.
Strong proficiency in Verilog/SystemVerilog RTL design.
Experience with one or more of the following protocols: PCIe, CXL, NVMe, USB.
Responsibilities
Develop synthesizable RTL for high-speed protocol, packet parsing, timestamping.
Perform synthesis, P&R, timing closure for high-end FPGAs.
Collaborate with hardware, firmware, and software teams.
Skills
Verilog/SystemVerilog RTL design
PCIe protocol knowledge
FPGA development
UVM knowledge
Scripting (Python, Tcl)
Education
BS in Electrical Engineering, Computer Science or Computer Engineering
MS in Electrical Engineering
Tools
Vivado
Quartus
ModelSim
Job description
A global technology company is seeking a Staff Logic Design Engineer in Milpitas, CA. The candidate will architect and implement high-performance digital logic for protocol analysis on FPGA-based systems, requiring 7+ years of experience in digital logic design and strong proficiency in Verilog/SystemVerilog. This role offers a competitive salary range of $141,900.00-$189,200.00 and requires collaboration with cross-functional teams to deliver innovative solutions.