Staff FPGA Logic Design Engineer - High-Speed Protocols

Teledyne; Milpitas (CA); On-site; USD 142,000 - 189,000; Full time

Job summary

Teledyne LeCroy is seeking a Staff Logic Design Engineer to architect and implement high-performance digital logic for protocol capture, analysis, and emulation on FPGA-based systems. You will work on real-time decoding of PCIe, USB, Ethernet, and other protocols, collaborating with cross-functional teams.

The role requires 7+ years in digital logic design for FPGA/ASIC, strong Verilog/SystemVerilog skills, and hands-on FPGA toolchains (Vivado, Quartus).

Qualifications

• BS in EE, CS or Computer Engineering required.
• MS in EE is a plus.
• 7+ years of experience in digital logic design for FPGA or ASIC.
• Strong proficiency in Verilog/SystemVerilog RTL design.
• Experience with PCIe protocol (Gen4/Gen5/Gen6).
• Hands-on with FPGA toolchains and timing closure.
• Knowledge of CDC, clock domain design, and reset strategies.

Responsibilities

• RTL design & microarchitecture for high-speed protocol and buffering.
• Develop synthesizable RTL for protocol capture, parsing, and timestamping.
• Integrate PCIe IP cores, DMA engines, and decoders.
• Build SystemVerilog/UVM testbenches for verification.
• Collaborate with hardware, firmware, and software teams.

Skills

Verilog/SystemVerilog RTL design

PCIe protocol

FPGA toolchains

UVM

CDC & clock domain design

Education

BS in EE/CS/Computer Engineering

MS in EE is a plus

Tools

Vivado

Quartus

ModelSim

Vivado Simulator

Job description

Teledyne LeCroy is seeking a Staff Logic Design Engineer to architect and implement high-performance digital logic for protocol capture, analysis, and emulation on FPGA-based systems. You will work on real-time decoding of PCIe, USB, Ethernet, and other protocols, collaborating with cross-functional teams.

The role requires 7+ years in digital logic design for FPGA/ASIC, strong Verilog/SystemVerilog skills, and hands-on FPGA toolchains (Vivado, Quartus).