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Espace, located in Saratoga, is seeking an experienced engineer to focus on FPGA RTL development in SystemVerilog or VHDL. This full-time role involves owning design architecture, collaborating on requirements, and leading verification activities.
The ideal candidate has over 10 years of experience, a Master’s degree in relevant fields, and familiarity with space environment designs. Competitive salaries and a commitment to sustainability are offered.
Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place! E‑Space is bridging Earth and space to enable hyper‑scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly‑advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space‑based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.
This is a full‑time, exempt position based out of our Saratoga office. The target base pay for this position is $100,000 – $200,000 annually. Compensation will be determined by relevant job‑related knowledge, skills, and experience. E‑Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role.