FPGA / VLSI Engineer

E-Space; Saratoga (CA); On-site; USD 120,000 - 220,000; Full time

Benefits offered by this job

Competitive salaries and paid time off

Health and wellness care options

Continuous learning and development opportunities

Financial solutions for the future and optional legal services

Job summary

E-Space is seeking a full-time FPGA/VLSI engineer at their Saratoga office to contribute to digital hardware development for ASIC/SoC platforms. Responsibilities include RTL design, FPGA prototyping, and simulation strategies. The ideal candidate will have a degree in Electrical Engineering, strong skills in SystemVerilog, and experience with FPGA development flows. The position offers a competitive salary range of $120,000 – $220,000 annually, along with benefits focusing on health, wellness, and continuous learning.

Qualifications

• Strong experience writing synthesizable SystemVerilog/Verilog.
• Proven experience with FPGA development flows, including synthesis, implementation, and validation.
• Solid understanding of digital design fundamentals and timing analysis.

Responsibilities

• Design and implement RTL using SystemVerilog with consideration for timing, power, and area.
• Perform FPGA prototyping, validation, and hardware bring‑up for digital designs.
• Develop and execute simulation and debugging strategies at block and subsystem levels.
• Contribute to SoC‑level integration, including interfacing with processors, memory, and peripherals.
• Analyze and resolve timing issues, including setup/hold violations and clock‑domain‑crossing concerns.

Skills

SystemVerilog

FPGA development

Digital design fundamentals

Education

Bachelor’s, Master’s, or PhD in Electrical Engineering or related field

Tools

Xilinx Zynq

Intel SoC FPGA

Job description

Overview

E-Space is building a highly-advanced low Earth orbit (LEO) space system to enable hyper-scaled deployments of Internet of Things (IoT) solutions. We are seeking an FPGA/VLSI engineer to contribute to digital hardware development for ASIC/SoC platforms used in advanced communication systems. This role focuses on RTL design, FPGA prototyping, simulation, debugging, and system integration, working closely with cross‑functional teams.

Responsibilities

• Design and implement RTL using SystemVerilog with consideration for timing, power, and area.
• Perform FPGA prototyping, validation, and hardware bring‑up for digital designs.
• Develop and execute simulation and debugging strategies at block and subsystem levels.
• Contribute to SoC‑level integration, including interfacing with processors, memory, and peripherals.
• Analyze and resolve timing issues, including setup/hold violations and clock‑domain‑crossing concerns.
• Collaborate with verification, ASIC, and software teams to ensure functional correctness and performance.
• Participate in design reviews and contribute to improving design quality and best practices.

Qualifications

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field.
• Strong experience writing synthesizable SystemVerilog/Verilog.
• Proven experience with FPGA development flows, including synthesis, implementation, and validation.
• Solid understanding of digital design fundamentals and timing analysis.

Preferred Skills

• Experience with SoC FPGA platforms such as Xilinx Zynq or Intel SoC FPGA.
• Familiarity with AXI/AHB or similar bus protocols.
• Exposure to ASIC design flow, including synthesis and static timing analysis.
• Experience with high‑speed interfaces such as PCIe or Ethernet.
• Knowledge of communication systems, e.g., 5G PHY/MAC concepts.

What Success Looks Like

• Independently handles well‑defined design blocks from RTL to FPGA validation.
• Produces clean, efficient, and timing‑aware RTL.
• Effectively debugs issues across simulation and hardware.
• Collages well within a team and contributes to overall project progress.
• Continuously improves technical depth and delivery efficiency.

Compensation & Location

This is a full‑time, exempt position based at our Saratoga office. The target base pay for this role is $120,000 – $220,000 annually. Total compensation will be determined by relevant work experience and knowledge.

Employment Sponsorship

E‑Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role.

Benefits

• Competitive salaries and paid time off.
• Health and wellness care options.
• Continuous learning and development opportunities.
• Financial solutions for the future and optional legal services (US only).