Staff Engineer, Serdes Analog Design

Samsungsemiconductor; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

401(k)

Job summary

PVH (Tommy Hilfiger/Calvin Klein) seeks an experienced IC Architect for Serdes and high‑speed interconnect design. You will work on architecture, circuits, and verification for Serdes IPs, clocking, and analog blocks across multiple interfaces, guiding layout teams, and validating silicon performance.

The role requires senior-level RF/Analog/Serdes expertise and collaboration across hardware teams, with a focus on power efficiency and reliability in advanced CMOS processes.

Qualifications

• Bachelor’s degree with 10+ years experience, or Master’s with 8+ years, or PhD with 5+ years.
• Minimum 2+ years experience in RF/Analog/Serdes SoC design.
• Knowledge of bandgap, LDO, filters.
• Knowledge of Serdes IP circuits (CTLE, DFE, FFE, clock distribution, PI, IQ generation).
• Knowledge of Serdes architecture and high-speed interconnect standards (USB, PCIe, UCIe).
• Knowledge of ESD, PLL, clock generation, ADC, DAC is a plus.

Responsibilities

• Architect and design Serdes transceivers and analog components.
• Develop high-performance, low-power Serdes for various interfaces (display, camera, UA‑link, Ethernet).
• Translate specifications into schematics and build testbenches for simulation.
• Supervise layout designers to ensure LVS/DRC-clean layouts.
• Validate silicon functionality and performance post-layout.

Skills

RF/Analog/Serdes design

Serdes IP circuits (CTLE, DFE, FFE, PI

Clock distribution

ESD, PLL, clock generation

Python, MATLAB

Team collaboration

Education

Bachelor’s degree with 10+ years experience

Tools

Cadence

Spectre

Totem

EMX

Job description

Location

Daily onsite presence at our San Jose, CA headquarters in alignment with our Flexible Work policy.

What you’ll do

In this role, you will actively work on the architecture and circuits of high‑speed interconnect transceivers (Serdes). Your responsibilities include designing circuits for Serdes IPs, clock generation, and traditional analog circuits; developing high‑performance, low‑power Serdes for display interface, camera sensor interface, UCIe/die‑to‑die interconnect, and 224/448Gbps UA‑link/Ethernet; using advanced CMOS process technologies to design low‑power, low‑voltage analog and custom digital components; translating component design specifications into schematics; building simulation test‑benches to evaluate circuit performance and reliability; supervising layout designers to generate LVS/DRC‑clean layout; optimizing layout to improve power consumption and performance; and validating functionality and performance in silicon.

What you bring

• Bachelor’s degree with 10+ years experience, or Master’s with 8+ years, or PhD with 5+ years.
• Minimum 2+ years experience in RF/Analog/Serdes SoC design.
• Knowledge and experience with analog circuits such as bandgap, LDO, and filters.
• Knowledge and experience with Serdes IP circuits such as CTLE, DFE, FFE, clock distribution, PI, and IQ generation.
• Knowledge of Serdes architecture and high‑speed interconnect standards (USB, PCIe, UCIe).
• Knowledge of ESD, PLL, clock generation, ADC, DAC is a plus.
• Proficiency with EDA tools (Cadence, Spectre, Totem, EMX).
• Comfortable with scripting languages (Python, MATLAB).
• Strong collaborative, inclusive, innovative, and learning‑oriented mindset.

What we offer

This position offers a competitive U.S. pay range and incentive opportunities tied to individual and company performance. Benefits include medical, dental, vision, 401(k) plans, and additional wellness and family support programs. The role also includes a flexible work environment, paid time off, and additional support for personal and family wellness.