Staff Engineer, High-Speed PCB Layout & SI/PI

Celestica Inc.

Austin, Northern (TX, KY)

Hybrid

USD 140,000 - 180,000

Full time

31 hours ago
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Job summary

Celestica Inc. in Austin, TX is seeking a Staff Engineer, Hardware Design (PCB Layout) to lead high-density PCB layout efforts and work with cross-functional teams to deliver robust designs.

You will mentor junior designers and drive manufacturability throughout the design process. The role emphasizes SI/PI optimization, PDN considerations, impedance control, and DFx-compliant layouts, collaborating with manufacturing, test, and reliability groups to ensure a first-pass yield and robust

Qualifications

  • 10+ years of dedicated PCB layout and design experience.
  • Experience with high-density multi-layer PCBs (12–28+ layers).
  • Familiar with IPC standards and EMI/EMC regulations.
  • Ability to summarize layout requirements from customers.

Responsibilities

  • Execute the layout, routing and component placement of high-density PCBs using Cadence Allegro.
  • Collaborate with mechanical, electrical and thermal engineers to optimize form factor and performance.
  • Ensure DFx guidelines are met and manage manufacturing release packages.
  • Support manufacturing, testing and qualification through product lifecycle.

Skills

Signal Integrity & Power Integrity
HDI PCB design
DFM/DFX/DFT knowledge
Cross-functional collaboration
EMC/EMI layout knowledge
PCB fabrication & PCBA assembly
IPC standards knowledge
IT platforms & database design
Visual/printable documentation
Strong communication

Education

Bachelor's degree in Electrical Engineering or related

Tools

Cadence Allegro 22.x+

Job description

Celestica Inc. in Austin, TX is seeking a Staff Engineer, Hardware Design (PCB Layout) to lead high-density PCB layout efforts and work with cross-functional teams to deliver robust designs.

You will mentor junior designers and drive manufacturability throughout the design process. The role emphasizes SI/PI optimization, PDN considerations, impedance control, and DFx-compliant layouts, collaborating with manufacturing, test, and reliability groups to ensure a first-pass yield and robust

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