Staff Digital Verification Engineer

Efficient Computer; San Jose (CA); On-site; USD 180,000 - 220,000; Full time

Job summary

A leading company in energy-efficient computing is seeking a Staff Digital Verification Engineer to verify innovative processor technology. This role involves writing UVM testbenches, analyzing coverage reports, and collaborating with design teams to enhance product quality. Join a culture that values impact, ownership, and professional growth while working on cutting-edge technology.

Benefits

401K match

Paid benefits

Equity

Parental leave

Flexible work arrangements

Qualifications

• Minimum 8+ years in design verification.
• Experience with SystemVerilog test benches.

Responsibilities

• Write modular UVM testbenches and tests for design verification.
• Collaborate with design teams to fix bugs and coverage gaps.

Skills

Design Verification

SystemVerilog

Python

Coverage-driven Verification

Constraint Random Testing

Education

Bachelor’s in Engineering

Master’s or PhD

Tools

UVM

OVM

Job description

Efficient is developing the world’s most energy-efficient general-purpose computer processor. Our patented technology uses 100x less energy than state-of-the-art commercially available ultra-low-power processors and is programmable with standard high-level programming languages and AI/ML frameworks. This efficiency enables perpetual, pervasive intelligence—running AI/ML continuously on a AA battery for 5-10 years. Our platform's unprecedented efficiency fosters a new computing revolution, especially in IoT devices that capture and curate first-party data.

Job Title: Staff Digital Verification (DV) Engineer

Efficient seeks a Staff DV Engineer who wants to influence the future of computing. You will verify our first-generation product's Fabric technology by writing UVM testbenches, analyzing coverage reports, and executing test plans. You will help develop internal processes for building robust, verified designs, especially as we scale to higher-performance products.

Key Responsibilities

1. Write modular UVM testbenches and tests for design verification.
2. Use constraint-random testing to stimulate devices and increase coverage.
3. Write SystemVerilog assertions to verify design invariants.
4. Refine code coverage with cover points/groups.
5. Collaborate with design teams to fix bugs and coverage gaps.
6. Support gate-level simulations for design signoff.
7. Assist third-party vendors and build verification dashboards.
8. Develop internal processes to improve code quality, coverage, and correctness.

Required Qualifications & Experience

1. Minimum 8+ years in design verification.
2. Experience with SystemVerilog test benches and components.
3. Bachelor’s in Engineering or related field; Master’s or PhD a plus.
4. Experience creating reusable verification infrastructure.
5. Proficiency in coverage-driven, constrained random verification.
6. Ability to analyze regressions for root causes.
7. Experience scripting with Python.
8. Knowledge of UVM/OVM and IEEE-1801 (UPF) flows is a plus.
9. Preferred: Knowledge of computer architecture, processor design, and development toolchains.

We offer a competitive salary ($180,000 - $220,000), equity, and benefits. Compensation depends on experience and location.

Why Join Efficient?

We value impact over hierarchy. Produce high-quality work, and you'll be recognized and rewarded. We foster ownership, autonomy, and professional growth. If you're ready to shape the future of high-performance computing, let's talk.

Our benefits include 401K match, paid benefits, equity, parental leave, and flexible work arrangements. We support personal and professional development.