Staff Digital Design Engineer — SoC RTL & IP Blocks

Infineon Technologies AG; San Jose (CA); Vor Ort; USD 134.000 - 184.000; Vollzeit

Benefits dieser Stelle

Incentive plan

Zusammenfassung

Infineon Technologies AG in San Jose is seeking a Staff Digital Design Engineer to join our Research & Development team, blending creativity with advanced engineering to shape the future of automotive and electronics. You will execute hands-on digital IP and SoC design, refine micro-architecture, implement RTL, and ensure release readiness across cross-functional teams.

The role emphasizes collaboration with Verification, Architecture, Physical Design, and System teams, including integrating

Qualifikationen

• Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering.
• 3+ years hands-on semiconductor digital IP design and RTL development.
• Strong SystemVerilog/Verilog RTL coding and digital design fundamentals.
• Experience with front-end flows (lint, CDC, synthesis) and verification.

Aufgaben

• Execute digital IP and SoC design including RTL implementation and release readiness.
• Develop synthesizable SystemVerilog/Verilog RTL for reusable IP blocks.
• Translate roadmap requirements into RTL deliverables and milestones.
• Drive design quality through lint, CDC, RDC, synthesis, and sign-off.
• Debug issues across block, integration, and system levels with cross-functional collaboration.

Kenntnisse

SystemVerilog RTL

Digital IP design

RTL development

Ethernet PHYs

Scripting (Python/Tcl/Perl)

Ausbildung

Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering

Tools

Lint

CDC

Synthesis

ATPG readiness

Jobbeschreibung

Infineon Technologies AG in San Jose is seeking a Staff Digital Design Engineer to join our Research & Development team, blending creativity with advanced engineering to shape the future of automotive and electronics. You will execute hands-on digital IP and SoC design, refine micro-architecture, implement RTL, and ensure release readiness across cross-functional teams.

The role emphasizes collaboration with Verification, Architecture, Physical Design, and System teams, including integrating