Senior SoC & IP Digital Design Engineer

Infineon Technologies AG; San Jose (CA); On-site; USD 134,000 - 184,000; Full time

Job summary

Infineon Technologies AG is seeking a Staff Digital Design Engineer to shape next-gen digital IP and SoC blocks in an R&D environment. You will deliver synthesizable SystemVerilog RTL, drive lint/CDC/RDC and sign-off processes, and work across verification, architecture and physical design teams to ensure robust integration.

The role emphasizes micro-architecture refinement, RTL release execution, and generator-based RTL flows to boost reuse and productivity, including automotive Ethernet PHY

Qualifications

• Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering or related field.
• 3+ years hands-on semiconductor digital IP design and RTL development.
• Strong SystemVerilog/Verilog RTL coding skills and a solid grasp of digital design fundamentals (FSMs, clock domain crossing, timing).
• Experience with micro-architecture definition, design documentation, integration support, and RTL release execution.
• Front-end design flows knowledge (lint, CDC, synthesis) and verification/debug activities.
• Knowledge of Ethernet protocols or networking IC development is preferred.
• Scripting experience (Python, Tcl, Perl) or exposure to generator-based RTL flows.

Responsibilities

• Execute hands-on digital IP and SoC design, including micro-architecture refinement and RTL release readiness.
• Develop high-quality synthesizable RTL in SystemVerilog/Verilog for reusable, configurable IP blocks.
• Translate IP and SoC roadmap requirements into design plans, RTL deliverables, milestones, risks, and closure actions.
• Drive design quality closure through lint, CDC, RDC, synthesis, DFT checks, ATPG readiness, and related sign-off activities.
• Debug and resolve design issues at block, integration, and system levels, working closely with Verification, Architecture, Physical Design, and System teams.
• Support development and integration of Automotive Base-T1 Ethernet PHYs.
• Contribute to IP architecture and design trade-off discussions.

Skills

SystemVerilog/Verilog RTL

RTL debugging

Automation with generator-based RTL

Python scripting

ISO 26262 familiarity

Education

Bachelor's or Master's in Electrical/Electronics/Computer Engineering

Job description

Infineon Technologies AG is seeking a Staff Digital Design Engineer to shape next-gen digital IP and SoC blocks in an R&D environment. You will deliver synthesizable SystemVerilog RTL, drive lint/CDC/RDC and sign-off processes, and work across verification, architecture and physical design teams to ensure robust integration.

The role emphasizes micro-architecture refinement, RTL release execution, and generator-based RTL flows to boost reuse and productivity, including automotive Ethernet PHY