Staff Digital Design Engineer

Infineon Technologies; San Jose (CA); On-site; USD 134,000 - 184,000; Full time

Job summary

Infineon Technologies AG is seeking a Staff Digital Design Engineer to shape next-gen digital IP and SoC blocks in an R&D environment. You will deliver synthesizable SystemVerilog RTL, drive lint/CDC/RDC and sign-off processes, and work across verification, architecture and physical design teams to ensure robust integration.

The role emphasizes micro-architecture refinement, RTL release execution, and generator-based RTL flows to boost reuse and productivity, including automotive Ethernet PHY

Qualifications

• Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering or related field.
• 3+ years hands-on semiconductor digital IP design and RTL development.
• Strong SystemVerilog/Verilog RTL coding skills and a solid grasp of digital design fundamentals (FSMs, clock domain crossing, timing).
• Experience with micro-architecture definition, design documentation, integration support, and RTL release execution.
• Front-end design flows knowledge (lint, CDC, synthesis) and verification/debug activities.
• Knowledge of Ethernet protocols or networking IC development is preferred.
• Scripting experience (Python, Tcl, Perl) or exposure to generator-based RTL flows.

Responsibilities

• Execute hands-on digital IP and SoC design, including micro-architecture refinement and RTL release readiness.
• Develop high-quality synthesizable RTL in SystemVerilog/Verilog for reusable, configurable IP blocks.
• Translate IP and SoC roadmap requirements into design plans, RTL deliverables, milestones, risks, and closure actions.
• Drive design quality closure through lint, CDC, RDC, synthesis, DFT checks, ATPG readiness, and related sign-off activities.
• Debug and resolve design issues at block, integration, and system levels, working closely with Verification, Architecture, Physical Design, and System teams.
• Support development and integration of Automotive Base-T1 Ethernet PHYs.
• Contribute to IP architecture and design trade-off discussions.

Skills

SystemVerilog/Verilog RTL

RTL debugging

Automation with generator-based RTL

Python scripting

ISO 26262 familiarity

Education

Bachelor's or Master's in Electrical/Electronics/Computer Engineering

Job description

#WeAreIn for jobs that impact everyone's lifeJoin the thinkers, builders, and problemsolvers behind tomorrow’s technology. As a Staff Digital Design Engineer in our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life.Are you in?Your roleKey responsibilities in your new roleExecute hands-on digital IP and SoC design, including micro-architecture refinement, RTL implementation, design documentation, integration support, and release readinessDevelop high-quality, synthesizable RTL in SystemVerilog/Verilog for reusable, configurable, integration-ready IP blocksTranslate IP and SoC roadmap requirements into design plans, RTL deliverables, milestones, risks, and closure actionsDrive design quality closure through lint, CDC, RDC, synthesis, DFT checks, ATPG readiness, and related sign-off activitiesDebug and resolve design issues at block, integration, and system levels, working closely with Verification, Architecture, Physical Design, and System teamsSupport development and integration of Automotive Base-T1 Ethernet PHYsUse automated, configurable, generator-based RTL flows to improve reuse, scalability, consistency, and productivityContribute to IP architecture and design trade-off discussionsYour profileQualifications and skills to help you succeedBachelor's or Master's degree in Electrical, Electronics, or Computer Engineering, or a related field3+ years of hands-on experience in semiconductor digital IP design and RTL developmentSolid SystemVerilog/Verilog RTL coding skills and a strong grasp of digital design fundamentals (FSMs, clock domain crossing, timing)Experience with micro-architecture definition, design documentation, integration support, and RTL release executionWorking knowledge of front-end design flows (lint, CDC, synthesis)Experience with verification and debug activities, including analyzing simulation failures and working with verification teamsUnderstanding of the chip development processKnowledge of Ethernet protocols or experience with networking IC development is preferredScripting experience (Python, Tcl, Perl) or exposure to generator-based RTL flowsFamiliarity with automotive standards (e.g., ISO 26262 functional safety)Infineon Technologies is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), gender identity, national origin, ancestry, citizenship, age, physical or mental disability, legally protected medical condition, family care status, military or veteran status, marital status, domestic partner status, sexual orientation, or any other basis protected by local, state, or federal laws.Employment at Infineon is contingent upon proof of your legal right to work in the United States under applicable law, verification of satisfactory references, successful completion of a background check and drug test, and signing all your on-boarding documents.In some instances, if applicable, U.S. export control laws require that Infineon obtain a U.S. government export license prior to releasing technologies to certain persons. This offer is contingent upon Infineon's ability to satisfy these export control laws as related to your employment and anticipated job activities. The decision whether or not to submit and/or pursue an export license to satisfy this contingency, if applicable, shall be at Infineon's sole discretion.Infineon Technologies takes data privacy and identity theft very seriously. As such, we do not request personally-identifiable information (PII) from applicants over the internet or electronically. Please kindly refrain from disclosing your PII electronically during the application process or to unauthorized websites that may purport to be Infineon or any of our affiliates.Salary pay information:In line with local legal requirements, indicative salary ranges are disclosed for selected locations where applicable.LocationIndicative salary rangeSan Jose, CA, United StatesWage range that the company expects to pay for a qualified candidate:US$133,800 – US$184,000In addition, all employees will be eligible to participate in an incentive plan.#WeAreIn for driving decarbonization and digitalization.As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.Are you in?We are on a journey to create the best Infineon for everyone.We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity.Our hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.Please let your recruiter know if you need any accommodations during the interview process.Learn more about our various contact channels and about Diversity & Inclusion at Infineon.