Staff Device Modeling Engineer — Hybrid (FinFET/PDK)

Intel; Santa Clara (CA); Hybrid; USD 150,000 - 285,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Paid time off

Job summary

Intel in Hillsboro, Oregon, with additional location in Santa Clara, California, seeks a Staff Device Modeling Engineer to advance circuit simulation and device models for next‑gen semiconductor tech. You will collaborate with cross‑functional teams to drive high‑quality modeling tools and PDK readiness, accelerating product delivery and maintaining Intel's leadership in the foundry space.

Key responsibilities include developing compact models (FinFET, GAAFET), conducting simulations, and

Qualifications

• 6+ years of industry experience in the semiconductor field.
• Hands-on experience with compact modeling for FinFET or GAAFET.
• Proficiency with Python for data analysis and automation.

Responsibilities

• Partner with technology leaders and PDK teams to align modeling with roadmaps.
• Validate simulation and modeling solutions to meet PDK milestones.
• Develop compact device models for transistor performance and layout effects.
• Perform statistical modeling and data analysis using Python.
• Explore self-heating and OMI modeling innovations.
• Collaborate across teams and geographies for integrated solutions.

Skills

FinFET/GAafET compact modeling

Python scripting

Statistical modeling

RF simulation

EM simulation

Design technology collaboration

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Ph.D. in Electrical Engineering

Tools

HSPICE

Spectre

ICCAP

MBP

Job description

Intel in Hillsboro, Oregon, with additional location in Santa Clara, California, seeks a Staff Device Modeling Engineer to advance circuit simulation and device models for next‑gen semiconductor tech. You will collaborate with cross‑functional teams to drive high‑quality modeling tools and PDK readiness, accelerating product delivery and maintaining Intel's leadership in the foundry space.

Key responsibilities include developing compact models (FinFET, GAAFET), conducting simulations, and