Semiconductor Device Modeling Engineer

Intel Corporation; Austin (TX); Hybrid; USD 150,000 - 285,000; Full time

Job summary

Intel Corporation in Santa Clara, CA, with additional locations including Austin, TX, is seeking a Semiconductor Device Modeling Engineer to join the Compact Device Modeling Group (CDMG) within Design Enablement. The role focuses on characterizing device behavior and generating/updating compact models for next-generation technologies to enable high-performance, data-centric products.

You'll work with Python or C and shell scripting, apply BSIM and other compact models, and collaborate across

Qualifications

• Master's degree in Electrical Engineering or related with 3+ years semiconductor industry experience.
• PhD in Electrical Engineering or related with 1 year industry or research experience focusing on semiconductor devices or processes.
• Hands-on experience in Python or C, Shell scripting.
• Course work in semiconductor device physics, process flow, layout and simple circuit design and simulation.
• Ability to work independently after ramp-up.

Responsibilities

• Characterize device behavior and generate/update device models for new technologies.
• Co-optimize Intel's process technology to meet diverse design needs.
• Ensure robust and accurate model simulations and verifications.
• Support test automation and model extraction workflows.

Skills

Python/C

Shell scripting

Education

Master's degree in Electrical Engineering or related

PhD in Electrical Engineering or related

Tools

Cadence design tools (Virtuoso, DRC, LVS)

HSPICE / SPECTRE

ICCAP or MBP

Job description

About The Team

The Compact Device Modeling Group (CDMG) is part of Intel's Design Enablement (DE) organization. DE is a key pillar in enabling Intel to deliver design, development, and manufacturing services that allow internal and external customers to bring winning products to the marketplace. Your work will directly enable design teams to get to market faster with leadership products based on innovative technologies.

Job Details

Job Description:

About The Team

The Compact Device Modeling Group (CDMG) is part of Intel's Design Enablement (DE) organization. DE is a key pillar in enabling Intel to deliver design, development, and manufacturing services that allow internal and external customers to bring winning products to the marketplace. Your work will directly enable design teams to get to market faster with leadership products based on innovative technologies.

As a member of CDMG, you will be at the forefront of co-optimizing Intel's state-of-the-art process technology, enabling customers with diverse design needs to deliver best-in-class products for data-centric applications.

As a Semiconductor Device Modeling Engineer, you will be responsible for characterizing device behavior and generating/updating device models for new technologies while ensuring robust and accurate model simulations.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• Master's degree in Electrical Engineering or a related discipline with a minimum of 3+ years of industry experience in the semiconductor field; OR
• PhD in Electrical Engineering or a related discipline with a minimum of 1 year of industry or research experience and a dissertation focused on semiconductor devices or processes.
• Hands-on experience in Python or C, Shell programming.
• Experience or course work in semiconductor device physics, process flow, layout and simple circuit design and simulation.
• The ability to work independently after the initial ramp-up time.

Preferred Qualifications

• A Ph.D. degree in electrical engineering or related discipline with 3 + years of industry experience in the semiconductor field.
• Experience in BSIM models and other compact models, extraction tools (ICCAP or MBP), and commercially available simulators. (example: HSPICE, SPECTRE, etc.)
• Understanding of corner, statistical and sub-circuit models and their usages.
• Understanding of layout effects and models.
• Understanding of basic analog and digital circuit blocks and model interaction.
• Hands-on experience in semiconductor device DC/CV characterization tools, techniques, and systems. Experience in test automation and RF/noise/reliability tests is a plus.
• Understanding of Aging Simulations and reliability methodologies and tools is a plus.
• Experienced in a Cadence design environment, including schematic capture, analog design environment, virtuoso layout design, DRC, LVS, and layout extractions.

Job Type

Experienced Hire

Shift

Shift 1 (United States of America)

Primary Location

US, California, Santa Clara

Additional Locations

US, Arizona, Phoenix, US, Oregon, Hillsboro, US, Texas, Austin

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US

$149,600.00 - 284,580.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.