Staff Analog Design Engineer

Elevatesemi; San Diego (CA); On-site; USD 145,000 - 195,000; Full time

Benefits offered by this job

100% Employer Paid Health Insurance

Unlimited Paid Time Off

Performance Bonuses

Free Lunch Catered in by Local Restaurants

Private Equity Options

Retirement Plans

Sabbatical Program

Tuition Reimbursement

Volunteer Days

Relocation Assistance

Conference Attendance Support

Biweekly Phone Stipend

Employee Assistance Program

Job summary

Elevatesemi in San Diego, CA is searching for a Staff Analog Design Engineer to take ownership of major analog circuit blocks and subsystems. You'll lead architecture decisions, provide mentorship to junior engineers, and contribute to high-quality silicon delivery.

This role requires extensive experience in analog IC design, and you will partake in designing complex high-speed circuits and drive architecture strategies. A robust benefits package accompanies a salary range of $145,000.00 to $195,000.00.

Qualifications

• 8+ years of professional experience in analog IC design.
• Deep expertise in analog CMOS circuit design and analysis.
• Proven understanding of the end-to-end IC development lifecycle.

Responsibilities

• Lead the design and simulation of complex high-speed CMOS ATE circuits.
• Own analog circuit blocks from architectural definition through validation.
• Provide technical guidance to Senior and entry-level engineers.

Skills

Analog CMOS circuit design and analysis

Feedback loop design

Stability analysis

Communication skills

Collaboration skills

Education

Bachelor’s degree in electrical engineering

Master's degree preferred

Tools

Analog and mixed signal EDA tools

Job description

At Elevate Semiconductor, we empower semiconductor and system test customers by creating world class ICs that tackle the industry’s most complex automated test equipment challenges. Our innovative team designs the lowest power, highest density solutions to reduce cost of test while pushing performance forward.

As a Staff Analog Design Engineer, you will serve as a technical owner for major analog circuit blocks and subsystems. You will drive architecture decisions, mentor junior engineers, and play a key role in delivering high quality silicon.

This role is based in San Diego, CA and requires the individual to be onsite five days per week.

Responsibilities

• Lead the design and simulation of complex high speed and precision CMOS ATE circuits
• Own analog circuit blocks from architectural definition through silicon validation
• Perform and review layout, verification, and post layout simulations including advanced corner analysis
• Drive mixed signal simulation strategy at channel and chip levels
• Develop innovative circuit architectures to achieve aggressive power, performance, and density targets
• Provide technical guidance and mentorship to Senior and entry level engineers
• Partner closely with test, applications, and manufacturing teams to ensure robust product delivery

Requirements

• Bachelor’s degree in electrical engineering; Master’s degree preferred
• 8+ years of professional experience in analog IC design
• Deep expertise in analog CMOS circuit design and analysis
• Strong experience with feedback loop design, stability analysis, and compensation techniques
• Proven understanding of the end to end IC development lifecycle
• Extensive hands on experience with industry standard analog and mixed signal EDA tools
• Strong collaboration and communication skills across cross functional teams

Benefits

• 100% Employer Paid Health Insurance (Medical, Dental, Vision)
• Unlimited Paid Time Off
• Performance Bonuses
• Free Lunch Catered in by Local Restaurants
• Private Equity Options
• Retirement Plans
• Sabbatical Program
• Tuition Reimbursement
• Volunteer Days
• Relocation Assistance
• Conference Attendance Support
• Biweekly Phone Stipend
• Employee Assistance Program

The salary range for this role is $145,000.00-$195,000.00. Starting salary will be aligned with your relevant experience and demonstrated capabilities during the interview process. Typically, candidates begin at the initial tier of our compensation range, with placement adjusted for candidates presenting extensive directly applicable experience.