Principal Analog Design Engineer

Elevate Semiconductor; San Diego (CA); Vor Ort; USD 175.000 - 240.000; Vollzeit

Benefits dieser Stelle

100% Employer Paid Health Insurance

Unlimited Paid Time Off

Performance Bonuses

Free Lunch Catered

Private Equity Options

Retirement Plans

Sabbatical Program

Tuition Reimbursement

Volunteer Days

Relocation Assistance

Conference Attendance Support

Biweekly Phone Stipend

Employee Assistance Program

Zusammenfassung

Elevate Semiconductor is looking for a Principal Engineer in Analog Design to lead the design of advanced ATE instrumentation circuits. This role involves hands-on development, mentoring junior designers, and collaboration with cross-functional teams. The ideal candidate has a Master's or PhD in Electrical Engineering and extensive experience in Analog/Mixed-Signal IC design. The position offers competitive benefits, including 100% employer-paid health insurance, unlimited PTO, and performance bonuses while being located in San Diego, CA.

Qualifikationen

• 20+ years of experience in Analog/Mixed-Signal IC design.
• Deep expertise in designing complex mixed-signal systems.
• Experience leading a team of senior analog designers.

Aufgaben

• Lead architecture and design of advanced ATE instrumentation circuits.
• Drive end-to-end ownership from concept to production.
• Mentor and elevate senior and junior designers.

Kenntnisse

High-voltage analog architectures

Precision CMOS design techniques

Mixed-signal IC design

Strong problem-solving skills

Communication skills

Ausbildung

Master’s degree or PhD in Electrical Engineering

Tools

MATLAB

Simulink

Verilog-A

Jobbeschreibung

At Elevate Semiconductor, we empower semiconductor and system test customers by creating world class ICs that tackle the industry’s most complex automated test equipment challenges. Our innovative team designs the lowest power, highest density solutions to reduce cost of test while pushing performance forward.

As a Principal Engineer in Analog Design at Elevate Semiconductor, you will operate at the highest level of technical leadership while remaining deeply hands-on in architecture and circuit design. This role is built for engineers who don’t just guide innovation, they actively drive it from concept through silicon and into production.

You will lead the definition and execution of next-generation ATE instrumentation solutions, with a strong focus on high-voltage analog, precision design, and digitally assisted architecture. Working across design, layout, and production test, you will take ownership of complex systems that push the limits of performance in noise, linearity, power, and area.

This is a highly visible role where your technical judgment, execution speed, and ability to influence across domains will directly shape product success and company direction.

This is a full-time, onsite position based in San Diego, CA.

Responsibilities

• Lead architecture, design, and hands‑on development of advanced ATE instrumentation circuits, including high‑voltage analog and precision references and high speed pin electronics.
• Drive end‑to‑end ownership from concept, modeling, and design through tapeout, validation, and production release. Architect innovative solutions balancing noise, linearity, power consumption, and silicon area for high‑performance applications.
• Design and guide development of key building blocks such as DACs, high current output drivers, high speed Tx and Rx, instrumentation amplifiers.
• Champion digitally assisted analog techniques to enhance performance, scalability, and robustness.
• Develop and validate behavioral and system models using Octave and Verilog‑A.
• Collaborate closely with layout, digital/VLSI, packaging, and test engineering teams to ensure first‑pass silicon success.
• Mentor and elevate senior and junior designers through technical leadership and design reviews.
• Influence design methodology, tools, and best practices to improve efficiency, reuse, and product quality.
• Partner cross‑functionally with product and operations teams to ensure designs meet real‑world production and customer requirements.
• Act as a technical anchor across multiple projects, driving alignment and execution in a fast‑paced environment.

Requirements

• Master’s degree or PhD in Electrical Engineering or related field.
• 20+ MSEE/15+ PhD years of experience in Analog/Mixed‑Signal IC design with a strong track record of successful silicon.
• Deep expertise in high‑voltage analog architectures and precision CMOS design techniques.
• Proven experience designing complex mixed‑signal systems including ADCs, DACs, PLLs/DLLs, regulators, amplifiers, and interface circuits.
• Proven track record of leading complex analog ASICs from architecture definition to full analog verification.
• Experience leading a team of senior analog designers.
• Strong background in digitally assisted analog design methodologies.
• Expertise in system and behavioral modeling using MATLAB, Simulink, and/or Verilog‑A.
• Demonstrated ability to architect solutions that meet aggressive performance targets across noise, linearity, power, and area.
• Solid understanding of AMS design flows, chip integration, and assembly considerations.
• Experience working cross‑functionally with layout, digital, and production test teams.
• Exceptional problem‑solving skills with the ability to navigate complex, multi‑variable design challenges.
• Strong communication skills with the ability to influence across engineering disciplines and organizational levels.

Benefits

• 100% Employer Paid Health Insurance (Medical, Dental, Vision)
• Unlimited Paid Time Off
• Performance Bonuses
• Free Lunch Catered in by Local Restaurants
• Private Equity Options
• Retirement Plans
• Sabbatical Program
• Tuition Reimbursement
• Volunteer Days
• Relocation Assistance
• Conference Attendance Support
• Biweekly Phone Stipend
• Employee Assistance Program

The salary range for this role is $175,000.00-$240,000.00. Starting salary will be aligned with your relevant experience and demonstrated capabilities during the interview process. Typically, candidates begin at the initial tier of our compensation range, with placement adjusted for candidates presenting extensive directly applicable experience.