Staff AI/ML Design Verification Engineer Analog/Mixed-Signal

Analog Devices, Inc.; Chandler (AZ); On-site; USD 110,000 - 150,000; Full time

Job summary

Analog Devices, Inc. is looking for a Staff Design Verification Engineer in Chandler, AZ. The role involves developing verification strategies for analog and mixed-signal ICs, improving efficiency through AI/ML techniques. Candidates should have a strong background in SystemVerilog, UVM, and Python, along with the ability to deliver verification through tape-out sign-off.

The position offers the chance to work on cutting-edge technology, requiring collaboration with design and test teams to ensure product quality and delivery.

Qualifications

• 7+ years of IC verification experience or PhD with 5+ years.
• Strong proficiency in SystemVerilog and UVM.
• Solid Python scripting skills and knowledge of formal verification.

Responsibilities

• Apply AI/ML methodologies for failure clustering and coverage optimization.
• Develop verification plans and achieve coverage closure.
• Support silicon correlation and compare simulation with lab measurements.

Skills

SystemVerilog

UVM

Python

AI/ML techniques

Formal verification

Education

MSEE or MSCE

PhD (with 5+ years of experience)

BSEE/BSCE (with equivalent depth)

Tools

Cadence tools

Xcelium

JasperGold

Job description

Analog Devices, Inc. is looking for a Staff Design Verification Engineer in Chandler, AZ. The role involves developing verification strategies for analog and mixed-signal ICs, improving efficiency through AI/ML techniques. Candidates should have a strong background in SystemVerilog, UVM, and Python, along with the ability to deliver verification through tape-out sign-off.

The position offers the chance to work on cutting-edge technology, requiring collaboration with design and test teams to ensure product quality and delivery.