Staff AI Chip Design Engineer - Hybrid

Cognichip, Inc.; Redwood City (CA); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Cognichip, Inc. is seeking a Staff Chip Design Engineer to advance RTL design and ML-assisted silicon workflows in a hybrid Redwood City setting.

You will collaborate with ML and software teams to build scalable design-to-production pipelines and deliver end-to-end silicon solutions. Ideal candidates bring 10–15 years of RTL design or mixed design/verification experience, strong SystemVerilog and Python, and proven ability to communicate complex concepts across disciplines.

Qualifications

• Masters in Computer Science, Electrical Engineering, or closely related field.
• 10-15 years of RTL design experience or mix of design and verification.
• Proficiency in SystemVerilog and Python.
• Excellent written and verbal communication, especially cross-disciplinary.
• Experience in a dynamic, research-heavy startup environment.
• Courses or projects in machine learning / deep learning.

Responsibilities

• Serve as domain experts embedding chip design into AI chip design assistants.
• Bridge research and production; collaborate with ML and SW teams to integrate models into scalable pipelines.
• Define data-processing pipelines, training orchestration, and evaluation frameworks for large-scale experiments.
• Analyze large datasets, experimental logs, simulation outputs, and traces to diagnose model behavior and surface failures.
• Publish and present findings; contribute to open-source projects and share internally/externally.

Skills

RTL design

SystemVerilog

Python

Communication

Startup environment

ML coursework

Education

Master's degree in CS/EE

Tools

Verilator

CocoTB

Yosys

OpenSTA

PCIe

Vivado

Vitis

Quartus

Job description

Cognichip, Inc. is seeking a Staff Chip Design Engineer to advance RTL design and ML-assisted silicon workflows in a hybrid Redwood City setting.

You will collaborate with ML and software teams to build scalable design-to-production pipelines and deliver end-to-end silicon solutions. Ideal candidates bring 10–15 years of RTL design or mixed design/verification experience, strong SystemVerilog and Python, and proven ability to communicate complex concepts across disciplines.