SRAM Design Engineer Intern — Hands-on Circuits & Simulation

Samsung Electronics America; San Jose (CA); On-site; USD 39,000 - 94,000; Full time

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Job summary

Samsung Semiconductor's SRAM Lab in San Jose is seeking an intern to support the development, simulation, and optimization of SRAM circuits in a fast-paced environment. You will contribute to full-stack SRAM projects—from architecture and schematic design to silicon-level verification—while researching novel architectures to boost efficiency.

Ideal candidates are pursuing a Masters or PhD in Electrical or Electronic Engineering, have at least one academic term remaining, and are familiar with

Qualifications

• Pursuing Masters, or PhD in Electrical or Electronic Engineering preferred.
• Must have at least 1 academic quarter/semester remaining.
• Basic understanding of CMOS circuit design and semiconductor devices physics.
• Familiarity with SRAM or memory design concepts is helpful.
• Experience with EDA tools such as Cadence Virtuoso, hspice, finesim and spectre.
• Proficiency in scripting languages (Python, Perl or TCL).

Responsibilities

• Assist design and simulation of SRAM circuits using industry-standard EDA tools.
• Perform transistor-level schematic design for SRAM bitcell, sense amplifiers and peripheral circuits.
• Conduct simulations to verify functionality, timing, power and reliability of SRAM design.
• Document design processes, simulation results, and findings in technical reports or presentations.
• Complete other responsibilities as assigned.

Skills

CMOS basics

SRAM memory design

Python/Perl/TCL

Team collaboration

Continuous learning

Education

Pursuing Masters/PhD in Electrical or Electronic Engineering

Tools

Cadence Virtuoso

HSPICE

Finesim

Spectre

Job description

Samsung Semiconductor's SRAM Lab in San Jose is seeking an intern to support the development, simulation, and optimization of SRAM circuits in a fast-paced environment. You will contribute to full-stack SRAM projects—from architecture and schematic design to silicon-level verification—while researching novel architectures to boost efficiency.

Ideal candidates are pursuing a Masters or PhD in Electrical or Electronic Engineering, have at least one academic term remaining, and are familiar with