SRAM Design Engineer – High-Performance CPU Cores

AMD; Boxborough (MA); Hybrid; USD 140,000 - 190,000; Full time

Job summary

AMD’s Cores Organization is seeking an experienced Physical Design Engineer to advance SRAM and memory structures for next‑gen CPU products. You will work with architecture, RTL, circuit, and physical design teams to balance performance, power, area, and schedule.

You will contribute to floorplanning, timing closure, and signoff activities while addressing complex design and tool challenges, drawing on Verilog RTL expertise and strong problem-solving skills.

Qualifications

• Experience with memory-centric physical implementation and SRAM design.
• Strong understanding of CPU architectures and design tradeoffs.
• Familiarity with Verilog RTL modifications for timing and power optimization.

Responsibilities

• Contribute to physical design and implementation of high-speed SRAM and memory structures.
• Collaborate with architecture, RTL, circuit, and physical design teams to optimize power, performance, and area.
• Perform floorplanning, placement, clock tree synthesis, routing, timing closure, and design optimization.
• Analyze and resolve implementation, timing, power, and signoff challenges.
• Develop creative solutions to complex design and tool-related problems.
• Contribute to methodology and flow improvements that increase design quality and efficiency.
• Create and deliver technical presentations, design reviews, and documentation for engineering teams and management.
• Support physical verification, extraction, reliability analysis, and design signoff activities.

Skills

High-speed SRAM design

Memory design

CPU architecture understanding

Verilog RTL proficiency

Scripting (Python/Tcl/Perl/C)

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science

Tools

Industry-standard EDA tools for physical design

Parasitic extraction tools

Clock tree synthesis tools

Job description

AMD’s Cores Organization is seeking an experienced Physical Design Engineer to advance SRAM and memory structures for next‑gen CPU products. You will work with architecture, RTL, circuit, and physical design teams to balance performance, power, area, and schedule.

You will contribute to floorplanning, timing closure, and signoff activities while addressing complex design and tool challenges, drawing on Verilog RTL expertise and strong problem-solving skills.