SRAM Design Automation Engineer — 2nm/Advanced Node

Rapidus Corporation US; City of Albany (NY); On-site; USD 130,000 - 285,000; Full time

Benefits offered by this job

Health, dental and vision insurance

Job summary

Rapidus Corporation is seeking an SRAM Design Automation Engineer to architect, develop, and scale automation flows for high-performance SRAM macros and memory compilers across cutting-edge SoCs.

Work spans circuit design, CAD/EDA, physical design, DTCO, and process technology, enabling first-time-right silicon on 2nm/1.4nm-class nodes, with a focus on 2nm enablement flows and AI/ML-driven design space exploration.

Qualifications

• BS/MS/PhD in Electrical Engineering or related field
• Experience with SRAM or memory circuit design, memory compilers, or custom-IC automation.
• Proficiency with Cadence Virtuoso and layout automation; Cadence SKILL or equivalent automation languages.
• Experience with Spectre/HSPICE/SPICE simulation environments; strong Linux/Unix scripting skills.

Responsibilities

• Develop and maintain SRAM memory compiler flows with configurable architectures and redundancy.
• Implement automation for schematic, layout, and abstract view generation using SKILL and custom infrastructure.
• Build scalable frameworks to support multiple device options (FinFET, nanosheet, multi-Vt, multi-height cells) and advanced assist techniques.
• Create robust post-processing scripts to generate timing, power, leakage, stability, reliability, and yield reports across PVT corners.

Skills

SRAM design

Memory compilers

Cadence SKILL

Spectre SPICE

Linux scripting

Education

BS/MS/PhD in Electrical Engineering

Tools

Cadence Virtuoso

Cadence SKILL

Spectre

HSPICE

Python

Job description

Rapidus Corporation is seeking an SRAM Design Automation Engineer to architect, develop, and scale automation flows for high-performance SRAM macros and memory compilers across cutting-edge SoCs.

Work spans circuit design, CAD/EDA, physical design, DTCO, and process technology, enabling first-time-right silicon on 2nm/1.4nm-class nodes, with a focus on 2nm enablement flows and AI/ML-driven design space exploration.