Macro Analog Design Engineer

Rapidus Corporation US; City of Albany (NY); On-site; USD 120,000 - 160,000; Full time

Benefits offered by this job

Health, Dental and Vision coverage

Job summary

Rapidus Corporation US is seeking a seasoned macro layout engineer to design memory, logic, and analog/mixed-signal blocks for advanced semiconductor tech. You’ll drive layout optimization considering DFM and reliability while coordinating with circuit and process teams through development phases from early design to volume ramp.

You will lead adoption of next-gen automation tools and push for AI/ML-driven design space exploration to improve efficiency and yield.

Qualifications

• 3+ years of hands-on macro/custom layout design experience.
• Experience with DRC/LVS-based verification flows.
• Knowledge of advanced process design rules and manufacturing constraints.
• Basic understanding of circuit operation.

Responsibilities

• Design macro and custom layouts for memory, logic, and analog/mixed-signal blocks.
• Contribute to layout verification and post-layout checks; ensure correlation with electrical results.
• Collaborate with circuit, process, and PDK teams to refine constraints and guidelines.
• Lead optimization by integrating circuit conditions with physical implementation requirements.
• Develop evaluation macros spanning circuit and layout domains.

Skills

Macro layout design

DRC/LVS verification

Layout optimization

Circuit variability analysis

Cross-functional collaboration

English communication

Education

Bachelor's degree in Semiconductor/Electrical Engineering

Tools

SPICE

DFM tools

Job description

Position Summary:

This position focuses on macro and custom layout design for evaluation macros, memory, logic, and analog/mixed-signal functional blocks in advanced semiconductor process and device development.

Through layout optimization considering PPA (Performance, Power, Area), reliability, manufacturability (DFM), and yield, the engineer contributes to the validation and advancement of process and device technologies.

The engineer will work closely with circuit designers, process/device teams, and PDK teams, and will play a key role throughout the development phases from early design through volume ramp.

About Rapidus:

Rapidus Corporation, founded in 2022, is Japan-led initiative to build a world-class advanced logic semiconductor foundry. With a bold vision to accelerate innovation, we are pioneering cutting-edge logic semiconductor research, development, design, and manufacturing to transform the global semiconductor industry.

Why Join Us:

You will play a central leadership role in building the world's most advanced 2nm and next-generation enablement ecosystem, shaping the foundation for future semiconductor innovation.

You will focus on the implementation stages (Synthesis and PnR) of the digital reference flow. Additionally, you will lead the adoption of next-generation automation tools, including AI/ML-driven DSE (Design space exploration)

Key Responsibilities:

Macro Layout (Primary Responsibility)

• Macro/custom layout design for memory, logic, and analog/mixed-signal functional blocks
• Layout variation design intended for device characterization and process validation
• Layout optimization considering DRC/LVS/DFM/DFY, EMIR, and reliability
• Layout design and revision control for test chips (TEGs) and evaluation macros
• Support correlation analysis between silicon results (electrical characteristics, reliability, yield) and layout conditions

Cross-Functional Collaboration

• Collaborate with circuit designers to define layout constraints reflecting circuit intent
• Work with process and device development teams to define evaluation conditions and viewpoints
• Provide feedback to PDKs, including design rules and layout guidelines
• Contribute to circuit design for memory, logic, or analog blocks
• Perform circuit simulation and variability analysis using SPICE or equivalent tools
• Take ownership of post-layout circuit verification
• Propose optimization by integrating circuit conditions and physical implementation conditions
• Lead development of evaluation macros spanning both circuit and layout domains

Required Qualifications

• Bachelor's degree or higher in Semiconductor Engineering, Electrical Engineering, Physics, or a related field
• 3+ years of hands-on experience in macro/custom layout design
• Experience with DRC/LVS-based verification flows
• Fundamental knowledge of advanced process design rules and manufacturing constraints
• Basic understanding of circuit operation

Preferred Qualifications

• Experience with advanced technology nodes (7nm or below, FinFET/GAA, etc.)
• Experience in memory or analog/mixed-signal circuit design
• Cross-functional experience with process and/or device development teams
• Ability to communicate technical topics effectively in English

Desired Attributes

• Strong technical curiosity and proactive approach to problem solving
• Ability to collaborate effectively with cross-functional teams
• Flexibility to work in fast-paced and uncertain advanced R&D environments
• Comprehensive Health, Dental and Vision coverage, fully at company's expense (no deductibles)