SRAM Design Engineer, New Grad – Shape the AI Chip Era

NVIDIA Corporation; Santa Clara (CA); Presencial; USD 116 000 - 190 000; Tempo integral

Resumo da oferta

NVIDIA's Digital IP (DIP) group in Santa Clara is seeking a SRAM circuit design engineer for new graduates starting in 2026. You will work on transistor-level SRAM design, layout supervision, verification, and debugger for SRAM macros, and contribute to SRAM compiler development using NVIDIA's compute resources.

The role emphasizes collaboration with SOC design partners to meet performance and cost goals while enabling silicon production.

Qualificações

• Master's degree or higher in Electrical Engineering (or equivalent).
• SRAM design experience with digital circuit design, layout, and validation on FinFET/nanosheet processes.
• Experience with single-port/dual-port or register file SRAM macros; self-timed logic & sense amplifiers.
• Familiarity with Cadence Virtuoso schematic and layout capture tools.
• Delivery of silicon IP into production.

Responsabilidades

• Embedded SRAM design: transistor-level circuit, layout, verification, and debug.
• SRAM compiler development: automate assembling and validating multiple macros.
• Explore future process nodes to optimize power, performance and area.
• Collaborate with SOC design partners to guide silicon test and productization.

Conhecimentos

SRAM design

Digital circuit design

Layout verification

Cadence Virtuoso

Formação académica

Master's degree in Electrical Engineering

Ferramentas

Cadence Virtuoso

Descrição da oferta de emprego

NVIDIA's Digital IP (DIP) group in Santa Clara is seeking a SRAM circuit design engineer for new graduates starting in 2026. You will work on transistor-level SRAM design, layout supervision, verification, and debugger for SRAM macros, and contribute to SRAM compiler development using NVIDIA's compute resources.

The role emphasizes collaboration with SOC design partners to meet performance and cost goals while enabling silicon production.