SRAM Design Engineer — AI-Driven IP & Compiler Innovation

NVIDIA Corporation; Santa Clara (CA); On-site; USD 116,000 - 190,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation in Santa Clara is seeking a skilled SRAM circuit designer to drive embedded SRAM design and compiler development for advanced silicon. You will collaborate with SOC design, silicon test, and productization teams to optimize power, performance, and area across next‑gen GPUs and AI accelerators.

The role requires a BSEE (or equivalent) with 2+ years in SRAM design (MSEE/PhD preferred), familiarity with Cadence Virtuoso, and a proactive approach to applying AI tools in daily

Qualifications

• BSEE minimum (or equivalent experience).
• MSEE or PhD with 2+ years SRAM design experience.
• Familiarity with Cadence Virtuoso schematic and layout capture tools.
• Willingness to use AI effectively in day-to-day tasks.
• Self-motivation, attention to detail, and good written, verbal, and presentation skills.

Responsibilities

• Embedded SRAM design: transistor-level circuit design, supervising layout, verification, and debug of SRAM macros.
• SRAM compiler development: coding automated assembly and validation of multiple SRAM macros.
• Advanced development: exploring future process nodes and optimizing power, performance, and area.
• Guiding SOC design, silicon test, and productization with partners and teams.

Skills

SRAM design

Circuit design

AI in day-to-day tasks

Self-motivation

Written and verbal communication

Education

BSEE (or equivalent)

MSEE or PhD with 2+ years SRAM design

Tools

Cadence Virtuoso

Job description

NVIDIA Corporation in Santa Clara is seeking a skilled SRAM circuit designer to drive embedded SRAM design and compiler development for advanced silicon. You will collaborate with SOC design, silicon test, and productization teams to optimize power, performance, and area across next‑gen GPUs and AI accelerators.

The role requires a BSEE (or equivalent) with 2+ years in SRAM design (MSEE/PhD preferred), familiarity with Cadence Virtuoso, and a proactive approach to applying AI tools in daily