Sr Principal Digital Design Engineer

NXP Semiconductors; Town of Montana (WI); On-site; USD 192,000 - 263,000; Full time

Benefits offered by this job

Health insurance

Dental insurance

Vision insurance

401(k)

Job summary

NXP Semiconductors is seeking a Senior Digital Design Engineer in San Jose to lead digital architecture and RTL development for automotive PMICs. You will drive verification, timing, and production release while coordinating with analog, verification, and systems teams to deliver high-quality mixed-signal solutions.

The role requires a strong RTL background, 10+ years, and leadership capabilities to guide projects from concept through silicon validation and ramp.

Qualifications

• Advanced degree and strong background in digital IC design and architecture.
• Experience with RTL design, verification, and mixed-signal contexts.
• Leadership in cross-functional teams and project execution.

Responsibilities

• Review product requirements, IP architecture, and implementation plans for PMICs.
• Define and implement digital architectures for mixed-signal PMICs with power/area goals.
• Lead RTL development, integration, timing closure, and silicon bring-up.
• Develop digital control, monitoring, diagnostics, and fault management for PMICs.
• Create RTL/microarchitecture specs using Verilog/SystemVerilog; ensure quality.
• Drive verification strategy: test planning, simulation, formal verification, coverage.
• Deliver IP solutions with traces, docs, and verification collateral.
• Track milestones, code coverage, defects, and conformance to design requirements.
• Support silicon debug, qualification, reliability, and production ramp.
• Mentor junior engineers and advance design methodologies.

Skills

Digital design fundamentals

Finite state machines

Clock-domain crossing

Low-power design techniques

RTL design (Verilog/SystemVerilog)

Synthesis/STA/EC/DFT

Formal verification

UVM

Assertions

Coverage-driven verification

Cross-functional leadership

Education

M.S. in Electrical Engineering, Computer Engineering, or related field

Tools

Cadence

Synopsys

Siemens EDA

Job description

Locations: San Jose (Holger Way)

Time Type: Full time

Posted On: Posted Today

Job Requisition ID: R-10065972

Job Title: Senior Digital Design Engineer

Role Summary

Lead digital architecture, design, verification, and implementation of next-generation Power Management ICs (PMICs) for automotive and industrial applications. Drive product execution from concept through RTL development, integration, silicon validation, qualification, and production release. Collaborate across analog, verification, validation, subsystem, SoC, applications, systems, product definition, and customer-facing teams to deliver high-quality mixed-signal solutions.

Job Responsibility

• Review product requirements, IP architecture specifications, programming models, microarchitecture, interfaces, and implementation plans for automotive and industrial PMIC applications.
• Define and implement digital architectures for mixed-signal PMICs, ensuring alignment with system, performance, quality, reliability, safety, power, and area requirements.
• Lead digital design activities from architecture definition through RTL development, integration, synthesis, timing closure, low-power implementation, silicon bring-up, and production release.
• Design and develop digital control, monitoring, telemetry, diagnostics, configuration, protection, power sequencing, and fault management functions for PMIC and power conversion products.
• Develop and review RTL, microarchitecture, and design specifications using Verilog/SystemVerilog and industry-standard design and quality checking tools.
• Drive verification strategy and execution, including test planning, simulation, formal verification, coverage analysis, regression management, and achievement of NXP quality and maturity standards.
• Deliver complete IP solutions, including RTL, verification collateral, supporting documentation, and requirements traceability from specification through implementation.
• Track development metrics including milestones, code and functional coverage, defect resolution, and compliance with design requirements.
• Support silicon debug, characterization, qualification, reliability validation, and production ramp activities.
• Mentor junior engineers and drive continuous improvement in design methodologies, automation flows, and engineering best practices.

Job Qualification

• M.S. in Electrical Engineering, Computer Engineering, or a related field required.
• Minimum 10 years of experience in digital IC design and development, including technical leadership and architecture responsibilities.
• Strong understanding of digital design fundamentals, finite state machines, clock-domain crossing, reset architecture, and low‑power design techniques.
• Expertise in RTL design using Verilog/SystemVerilog for complex digital and mixed‑signal ICs.
• Experience with synthesis, static timing analysis, equivalence checking, DFT, and physical implementation flows.
• Strong knowledge of modern verification methodologies, including UVM, assertions, formal verification, and coverage‑driven verification.
• Experience developing digital controllers for PMICs, power management systems, automotive electronics, or industrial applications is highly desirable.
• Proficiency with industry‑standard EDA tools from Cadence, Synopsys, and Siemens EDA.
• Strong analytical and problem‑solving skills with the ability to develop innovative solutions for complex technical challenges.
• Excellent written and verbal communication skills with proven ability to lead cross‑functional teams in a fast‑paced product development environment.

NXP Introduction

NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets.

For more information, please visit our website NXP

Career Development Opportunities

Bright Minds. Bright Futures.

We believe that a key component to growing our business is to develop our people. To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills. Visit our careers website for more job information.

Commitment At NXP

We recognize NXP is a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year‑on‑year progress. Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality.

Salary Information

The base salary range for this position is as mentioned below per year. We also provide competitive benefits, incentive compensation, and/or equity for certain roles. Company benefits include health, dental, and vision insurance, 401(k), and paid leave. Please note that the base salary range (OR hourly rate) is a guideline, and individual total compensation may vary based on a number of factors such as qualifications, skill level, work location, and other business and organizational needs. This base pay range is specific to California and is not applicable to other locations. A reasonable estimate of the base salary range as of the date of this posting is:

• Company benefits include health, dental, and vision insurance, 401(k), and paid leave.

$191,500 to $263,300 annually

Equal Opportunity Employer

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.

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Locations: San Jose (Holger Way)