Sr Principal Application Engineer

Cadence Design Systems, Inc.; San Jose (CA); On-site; USD 148,000 - 276,000; Full time

Job summary

Cadence Design Systems, Inc. is seeking a Sr Principal Application Engineer in San Jose, CA to lead backend digital design implementation efforts across synthesis, place and route, and signoff.

You will drive PPA improvements, mentor teams, and collaborate with R&D and customers to optimize flows from RTL to GDSII. You will apply Tcl/Python scripting to automate processes, support flagship tapeouts, and push innovative techniques in SoC design for sub-5nm technologies.

Qualifications

• MS degree in Computer Science/Engineering, Electrical, Engineering, or related field.
• 10+ years industry experience in backend digital implementation.
• Experience with IC digital implementation flows and EDA tools.

Responsibilities

• Lead campaigns and strategies in RTL to GDSII digital implementation.
• Push Power, Performance and Area (PPA) improvements.
• Support flagship product tapeouts and collaborate with R&D to enhance flows.

Skills

Digital Design Fundamentals

Static Timing Analysis

Synthesis/Place & Route

RTL to GDSII

Tcl/Python scripting

Education

MS degree in Computer Science/Engineering/Electrical Engineering

Tools

Genus

Innovus

Conformal

Tempus

Modus

Voltus

Job description

Sr Principal Application Engineer### Sr Principal Application EngineerApply: SAN JOSE: Full time: Posted Today: R57124## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.****Job Description****Key Responsibilities** Hands-on work with Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Synthesis, Place and Route, Design Closure, and timing/power signoff, RTL to GDSII.Lead technical campaigns and strategies in the RTL to GDSII digital implementation space. Aggressively push Power, Performance, and Area (PPA) Deliver technical presentations and lead discussions internally and with customers. Work closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requirements with high quality.Support execution on critical customer flagship product tape outs.Amend and augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows. **Job Requirements** **Minimum**MS degree Computer Science/Engineering, Electrical, Engineering, or related field, plus 10+ years industry experience.Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required.Prior experience with IC digital implementation flows and backend EDA tools including Synthesis, Place and Route, IR Drop, backend design timing and power closure, RTL to GDSII.Experience in scripting in Perl/Tcl/Python to automate and implement process improvement is a must.Floor planning and power planning for System-on-Chip (SoC) designs with low powerMS degree Computer Science/Engineering, Electrical, Engineering, or related field, plus 10+ years industry experience.Prior experience with IC digital implementation flows and front-end EDA tools including Synthesis, DFT, and Logical Equivalence CheckingGood hands-on experience of Floorplanning, Place and Route, Timing analysis and Sign-off, preferable with CDNS tools suiteAdvanced clock tree synthesis techniques including SoC Clock Distribution, Clock Mesh, H-TreeMultiple design closure including Timing, DRC, LVS, and EMIR preferred.Experience with advanced technology nodes including Sub 5nm and below.Develop, debug, and optimize various aspects of design flows for SoC’s to achieve best Power, Performance and Area (PPA)Strong customer-facing communication and problem-solving skillsStrong personal drive for continuous learning and expanding professional skillsets.Strong verbal, written, and customer communication skills.Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, and/or Voltus is highly desired.*The annual salary range for California is $148,400 to $275,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.*