SR Layout Engineer, DEG

1000 Micron Technology, Inc.; Boise (ID); On-site; USD 80,000 - 100,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

Paid family leave

Robust paid time-off program

Paid holidays

Job summary

1000 Micron Technology, Inc. in Boise, Idaho, is seeking a Layout Engineer to design high-quality physical layouts for DRAM technologies. This role requires experience with Cadence Virtuoso and knowledge of verification methods such as DRC and LVS.

Candidates should have a strong grasp of analog layout fundamentals and experience with critical analog blocks. The position offers comprehensive benefits, including medical, dental, vision, and paid time off.

Qualifications

• Experience performing physical layout using Cadence Virtuoso or similar tools.
• Familiarity with DRC, LVS, physical verification, and reliability checks.
• Good understanding of circuit-design principles to create high-performance layouts.

Responsibilities

• Design and develop IP layouts used in DRAM chips.
• Perform layout verification such as LVS, DRC, and quality checks.
• Deliver block-level layouts on time with acceptable quality.

Skills

Physical layout using Cadence Virtuoso

DRC and LVS verification

Circuit-design principles

Analog layout fundamentals

Job description

Overview

Micron Technology is a world leader in memory and storage solutions. Our DRAM Engineering Group drives the physical implementation behind Micron’s most advanced memory products. We are seeking a Layout Engineer to build high‑quality physical designs for our DRAM technologies, managing multiple projects and collaborating with global teams.

Responsibilities

• Design and develop IP layouts used in DRAM chips.
• Perform layout verification such as LVS, DRC, EM, quality checks, and documentation.
• Deliver block‑level layouts on time with acceptable quality.
• Guide and review team‑members’ execution of sub‑block layouts.
• Contribute to effective project management.
• Communicate with engineering teams in the US, India, Japan, and other global locations to ensure project success.

Minimum Qualifications

• Experience performing physical layout using Cadence Virtuoso or similar tools.
• Familiarity with DRC, LVS, physical verification, and reliability checks.
• Good understanding of circuit‑design principles and ability to create high‑performance layouts that are area optimal.
• Hands‑on experience designing critical analog blocks such as temperature sensors, PLL, ADC, DAC, LDO, bandgap, reference generators, charge pumps, current mirrors, comparators, and differential amplifiers.
• Strong grasp of analog‑layout fundamentals (matching, electromigration, latch‑up, coupling, crosstalk, IR‑drop, active and passive parasitic devices).

Preferred Qualifications

• Experience with DRAM, memory circuits, or large‑scale hierarchical designs.
• Background in parasitic extraction flows and post‑layout optimization.
• Hands‑on experience with partial custom layout of devices and small analog blocks.
• Strong communication skills supporting global engineering collaboration.

Benefits

Micron provides medical, dental, and vision plans; income protection; paid family leave; a robust paid time‑off program; and paid holidays. For more detail see Micron’s Benefits Guide.

Equal Opportunity Statement

Micron is an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.