Layout Engineer, DEG

1000 Micron Technology, Inc.; Boise (ID); On-site; USD 80,000 - 120,000; Full time

Job summary

1000 Micron Technology, Inc. is seeking a Layout Engineer based in Boise, Idaho. This position involves building block-level layouts in Cadence Virtuoso while ensuring compliance with DRC, LVS, density, and reliability standards. The ideal candidate should have strong hands-on design abilities and experience working closely with global design teams.

Micron offers benefits aimed at health, peace of mind, and future preparation. Enjoy a robust paid time-off program and an equal opportunity workplace.

Qualifications

• Experience performing physical layout using Cadence Virtuoso or similar tools.
• Familiarity with DRC, LVS, physical verification, and reliability checks.
• Ability to plan, document, and review layout goals with cross-site teams.

Responsibilities

• Build block-level layouts in Cadence Virtuoso including floorplanning, placement, routing, and optimization.
• Ensure DRC, LVS, density, and reliability compliance.
• Support parasitic extraction, post-layout verification, and ECO activities.

Skills

Physical layout experience

Experience with Cadence Virtuoso

Familiarity with DRC and LVS

Strong communication skills

Job description

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our layout engineering team drives the physical design foundations behind Micron’s industry‑leading memory technologies. We work closely across global design, CAD, and verification groups, solving sophisticated challenges and enabling the performance and scalability our products rely on! We’re looking for a Layout Engineer who enjoys hands‑on design work and close collaboration.

Responsibilities

• Build block‑level layouts in Cadence Virtuoso including floorplanning, placement, routing, and optimization.
• Apply layout methods and physical constraints such as PDN, pin placement, routing blockages, and hierarchy.
• Ensure DRC, LVS, density, and reliability compliance.
• Support parasitic extraction, post‑layout verification, and ECO activities.
• Create partial custom layouts for selected device‑level or small analog blocks.

Minimum Qualifications

• Experience performing physical layout using Cadence Virtuoso or similar tools.
• Familiarity with DRC, LVS, physical verification, and reliability checks.
• Ability to plan, document, and review layout goals with cross‑site teams.

Preferred Qualifications

• Experience with DRAM, memory circuits, or large hierarchical designs.
• Background in parasitic extraction flows and post‑layout optimization.
• Hands‑on experience with partial custom layout for devices or small analog circuits.
• Strong communication skills supporting global engineering teams.

Benefits

Micron benefits are designed to help you stay well, provide peace of mind, and help you prepare for the future. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, includes paid family leave, and offers a robust paid time‑off program and paid holidays.

Equal Opportunity Employer

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.