Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

SPACE EXPLORATION TECHNOLOGIES CORP; Bastrop (TX); On-site; USD 115,000 - 160,000; Full time

Job summary

SPACE EXPLORATION TECHNOLOGIES CORP in Bastrop, TX, is looking for a Sr. Full Chip Physical Verification Engineer to join our teams in developing advanced silicon solutions for exciting projects like Starlink. The successful candidate will demonstrate proficiency in physical design flows, DRC, LVS, and ESD verification and possess a Bachelor’s in Electrical Engineering or Computer Science. This role requires a proactive, detail-oriented engineer ready to contribute to high-performance designs in a collaborative environment, with opportunities to work on cutting-edge technologies in space connectivity.

Qualifications

• 5+ years of ASIC and/or physical design flow development experience.
• Deep understanding of SOC top level physical design flows.
• Hands-on proficiency with DRC, LVS, PERC, and ESD verification.

Responsibilities

• Execute full-chip DRC, LVS, ESD, PERC signoff using industry standard tools.
• Maintain and optimize physical verification flows for advanced node SoCs.
• Develop and implement foundry Design Rule Manuals (DRM).
• Coordinate signoff across block and top-level design teams.

Skills

ASIC design experience

Physical verification methodologies

Calibre proficiency

Problem-solving skills

Education

Bachelor’s degree in electrical engineering or computer science

Tools

Calibre

IC Validator

Pegasus

Job description

Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

Bastrop, TX

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best‑in‑class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world‑class cross‑disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting‑edge next‑generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting‑edge solutions that will expand the performance and capabilities of the Starlink network.

RESPONSIBILITIES

• Own and execute full‑chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools like Calibre, ICV, or Pegasus
• Develop, maintain, and optimize physical verification flows for advanced node SoC’s.
• Interpret and implement foundry Design Rule Manuals (DRM) – translate rule updates into verified flow changes
• Debug and resolve complex DRC/LVS violations across hierarchical full‑chip designs
• Perform ESD verification – validate protection strategies, current paths, and CDM/HBM compliance
• Drive tapeout readiness by coordinating signoff across block and top‑level and Hard IP design teams
• Engage directly with foundry teams to resolve DRM ambiguities and waiver requests.
• Develop/modify design flows as needed to meet the overall design quality of results and chip integration requirements. Leverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows

BASIC QUALIFICATIONS

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 5+ years of ASIC and/or physical design flow development experience in industry

PREFERRED SKILLS AND EXPERIENCE

• Experience and deep understanding of SOC top level physical design flows (floor‑planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation)
• Experience in IP integration (e.g. memories, I/O’s, analog IPs, SerDes, DDR etc.)
• Deep expertise in DRC, LVS, PERC and ESD verification methodologies
• Hands‑on proficiency with Calibre, ICV (IC Validator), or Pegasus
• Direct foundry DRM experience – able to read, interpret, and implement complex rule decks
• Experience at advanced nodes (4nm and below)
• Experience with large SOC designs (>10M gates) with frequencies in excess of 1GHz
• Self‑driven individual with a can‑do attitude, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS

• Ability to work extended hours and weekends as needed to meet critical project milestones
• To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.