Sr ASIC Packaging Engineer [ Remote ]

WarmStart Ltd; Burlington, Northern (VT, KY); Hybrid; USD 120,000 - 190,000; Full time

Job summary

Encore Semi, Inc. in Burlington, VT is seeking a Sr ASIC Packaging Engineer to lead the physical architecture of high‑performance silicon in a fully remote role.

You will manage the silicon‑to‑board interface and ensure designs meet signal integrity, thermal, and reliability standards through expert simulation and innovative manufacturing techniques. Responsibilities include 3D EM simulations with HFSS, optimizing bump‑to‑ball transitions and high‑speed SerDes paths with ADS, and developing

Qualifications

• 10+ years in Electronics Packaging, specifically focused on high-bump-count ASICs and high-speed interfaces.
• B.S./M.S. in Electrical Engineering, Mechanical Engineering, or Materials Science.

Responsibilities

• Lead full-wave 3D electromagnetic simulations using ANSYS HFSS for ASIC package extractions.
• Optimize bump-to-ball transitions and high-speed SerDes paths using Agilent ADS.
• Design and develop advanced ASIC packaging solutions, including 2.5D/3D IC (HBM/CoWoS), Flip-Chip BGA, and Fan-Out Wafer-Level Packaging (FOWLP).
• Drive the Integration and Test phase by correlating simulation models with physical hardware measurements (VNA/TDR).
• Utilize Additive Manufacturing to develop custom heat sinks, interposers, or rapid-prototype substrates, reducing the R&D cycle for complex ASIC form factors.

Skills

HFSS

ADS

2.5D/3D packaging

HBM/CoWoS

Flip-Chip BGA

VNA/TDR

Education

B.S./M.S. in Electrical Engineering, Mechanical Engineering, or Materials Science

Job description

Encore Semi, Inc., Burlington, VT 05401 Remote

Job Description:

Encore Semi, Inc. is looking for a Sr ASIC Packaging Engineer to lead the physical architecture of high-performance silicon in a fully remote position. The role involves managing the silicon-to-board interface and ensuring that advanced ASIC designs meet rigorous signal integrity, thermal, and reliability standards through expert simulation and innovative manufacturing techniques.

Responsibilities:

• Lead full-wave 3D electromagnetic simulations using ANSYS HFSS for ASIC package extractions.
• Optimize bump-to-ball transitions and high-speed SerDes paths using Agilent ADS.
• Design and develop advanced ASIC packaging solutions, including 2.5D/3D IC (HBM/CoWoS), Flip-Chip BGA, and Fan-Out Wafer-Level Packaging (FOWLP).
• Drive the Integration and Test phase by correlating simulation models with physical hardware measurements (VNA/TDR).
• Utilize Additive Manufacturing to develop custom heat sinks, interposers, or rapid-prototype substrates, reducing the R&D cycle for complex ASIC form factors.

Qualifications:

• 10+ years in Electronics Packaging, specifically focused on high-bump-count ASICs and high-speed interfaces.
• B.S./M.S. in Electrical Engineering, Mechanical Engineering, or Materials Science.

Skills:

• Expert proficiency in ANSYS HFSS and Agilent ADS for package-level SI/PI analysis.
• Deep understanding of substrate materials (ABF, Coreless), thermal interface materials (TIMs), and underfill chemistry.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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