Satellite FPGA Design Engineer – DSP & SDR Focus

Kepler Communications Inc.

United States

Remote

USD 93.000 - 128.000

Vollzeit

Vor 4 Tagen
Sei unter den ersten Bewerbenden

Eine vollständige Bewerbung in einer Minute

Maßgeschneiderter Lebenslauf und Anschreiben – versandbereit.

Schaffe es an den ATS-Filtern vorbei

Benefits dieser Stelle

Accommodation during recruitment

Zusammenfassung

Kepler Communications seeks an experienced FPGA design engineer to craft FPGA code for satellite digital payloads and DSP-based software-defined radio interfaces. You will drive DSP-oriented FPGA implementations and interfacing with processors and peripherals.

You will participate in all stages of the FPGA design flow—from simulation to hardware testing—while ensuring timing closure and robust verification for space-grade hardware.

Qualifikationen

  • Bachelor’s Degree in Computer Engineering, Electrical Engineering, or equivalent with 5+ years of FPGA/RTL design experience.
  • Proficiency in Verilog, SystemVerilog, or VHDL, and experience with Xilinx FPGAs (Zynq, UltraScale).
  • Strong scripting skills (Python, Tcl, csh/bash) and experience with FPGA tools (Vivado, Quartus) and simulation tools (ModelSim).

Aufgaben

  • Design and implement FPGA code for satellite digital payloads, focusing on DSP algorithms for software-defined radio or embedded systems interfacing with processors and peripherals.
  • Participate in all phases of FPGA design flow including simulation, synthesis, place & route, timing closure, and hardware testing.

Kenntnisse

FPGA/RTL design
DSP algorithms
Verilog/SystemVerilog/VHDL
Python scripting

Ausbildung

Bachelor’s Degree in Computer Engineering or Electrical Engineering

Tools

Vivado
Quartus
ModelSim

Jobbeschreibung

Kepler Communications seeks an experienced FPGA design engineer to craft FPGA code for satellite digital payloads and DSP-based software-defined radio interfaces. You will drive DSP-oriented FPGA implementations and interfacing with processors and peripherals.

You will participate in all stages of the FPGA design flow—from simulation to hardware testing—while ensuring timing closure and robust verification for space-grade hardware.

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