SoC UPF Methodology Engineer

Apple Inc.; San Diego (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Apple Inc. is seeking a senior engineer in the Low Power group to advance UPF design and verification for next-generation chips. You will work on refining UPF workflows and ensuring seamless integration across mobile products.

Join a team exploring AI/ML approaches to optimize power-aware design and verification, with responsibilities spanning FE and P&R stages and close collaboration with design and verification teams.

Qualifications

• Bachelor's degree in a relevant field with at least 10 years of industry experience.

Responsibilities

• Enhance power intent coverage via static and dynamic verification techniques.
• Develop tailored UPF solutions to align with project requirements.
• Oversee UPF deployment and sign-off for frontend (FE) and place-and-route (P&R) stages.
• Conduct thorough power intent assessments on custom circuitry.
• Partner with design and verification teams to troubleshoot UPF workflow challenges.
• Integrate AI/ML technologies to optimize UPF processes and methodologies.

Skills

UPF verification

Python

Tcl

AI/ML in workflow

CMOS power design

RTL-to-GDSII flow

Cross-functional collaboration

Education

Bachelor's degree in a relevant field

Job description

Are you passionate about crafting solutions to intricate challenges? Join the Low Power group at Silicon Technologies and contribute to the development of cutting-edge technology and capabilities for low-power chip design. Your work will fuel Apple’s next-generation chips! You’ll play a crucial role in exploring AI/ML to design the workflow for the next generation of UPF. Additionally, you’ll refine our existing UPF framework and ensure its seamless integration and rigorous verification across our mobile products.

Description

• Enhancing power intent coverage via advanced static and dynamic verification techniques.
• Developing tailored UPF solutions to align with unique project requirements.
• Overseeing UPF deployment and sign-off for frontend (FE) and place-and-route (P&R) stages.
• Conducting thorough power intent assessments on custom circuitry.
• Partnering with design and verification teams to troubleshoot and fix UPF-related workflow challenges.
• Integrating AI/ML technologies to optimize UPF processes and methodologies.

Minimum Qualifications

• A minimum of a bachelor's degree in relevant field and a minimum of 10 years of relevant industry experience.

Preferred Qualifications

• Expertise in UPF implementation and verification.
• Proficiency in scripting with languages like Python and Tcl.
• Understanding of CMOS power design principles.
• Experience applying AI/ML to coding and workflow optimization.
• Knowledge of multi-voltage static verification tools (e.g., VSILP/VCLP, CLP).
• Familiarity with the complete RTL-to-GDSII design flow.
• Strong communication abilities for effective collaboration across multidisciplinary teams.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.

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Apple accepts applications to this posting on an ongoing basis.