SoC UPF Methodology Engineer

Anysilicon; Austin (TX); Hybrid; USD 120,000 - 170,000; Full time

Job summary

Silicon Technologies in Austin, TX is seeking a Power UPF Engineer to advance UPF methodologies for low-power chip designs powering Apple’s next-generation products. You will enhance power intent coverage, develop tailored UPF solutions, and oversee UPF sign-off for FE and P&R stages across complex SOCs.

Qualifications include a Bachelor’s degree and at least 3 years in the industry. Proficiency in Python/Tcl, CMOS power design, and experience applying AI/ML to optimization are highly valued.

Qualifications

• Bachelor's degree in a relevant field.
• Minimum of 3 years of relevant industry experience.

Responsibilities

• Enhance power intent coverage using advanced static and dynamic verification techniques.
• Develop tailored UPF solutions to meet unique project requirements.
• Oversee UPF deployment and sign-off for FE and P&R stages.
• Conduct thorough power intent assessments on custom circuitry.
• Collaborate with design and verification teams to troubleshoot UPF-related workflow challenges.
• Integrate AI/ML technologies to optimize UPF processes and methodologies.

Skills

UPF implementation

Python & Tcl

CMOS power design

AI/ML for workflow

Static verification tools

RTL-to-GDSII flow

Cross-functional communication

Education

Bachelor's degree in a relevant field

Tools

VSILP/VCLP/CLP

Job description

Join the Low Power group at Silicon Technologies to contribute to the development of innovative low-power chip designs that will power Apple's next-generation products. As a Power UPF Engineer, you will enhance Unified Power Format (UPF) methodologies and ensure rigorous verification across mobile SOCs, integrating AI/ML technologies to optimize processes.

Responsibilities:

• Enhance power intent coverage using advanced static and dynamic verification techniques.
• Develop tailored UPF solutions to meet unique project requirements.
• Oversee UPF deployment and sign-off for frontend (FE) and place-and-route (P&R) stages.
• Conduct thorough power intent assessments on custom circuitry.
• Collaborate with design and verification teams to troubleshoot UPF-related workflow challenges.
• Integrate AI/ML technologies to optimize UPF processes and methodologies.

Qualifications:

• Bachelor's degree in a relevant field.
• Minimum of 3 years of relevant industry experience.

Skills:

• Expertise in UPF implementation and verification.
• Proficiency in scripting languages such as Python and Tcl.
• Understanding of CMOS power design principles.
• Experience applying AI/ML to coding and workflow optimization.
• Knowledge of multi-voltage static verification tools (e.g., VSILP/VCLP, CLP).
• Familiarity with the complete RTL-to-GDSII design flow.
• Strong communication skills for effective collaboration across multidisciplinary teams.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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