SoC Physical Design Verification Engineer

Apple Inc.; Beaverton (OR); On-site; USD 120,000 - 160,000; Full time

Job summary

A leading company is seeking a SoC Physical Design Verification Engineer to join their Silicon Technologies group. In this role, you'll be responsible for ensuring rigorous physical verification of high-performance, efficient processors. Ideal candidates will have a BS degree, industry experience, and knowledge of physical design processes.

Qualifications

• Minimum BS and 3+ years of relevant industry experience.
• Experience with physical verification flows: DRC/LVS/ANT/HVDRC signoff.
• Tapeout experience with a track record of successful signoff.

Responsibilities

• Perform physical verification checks at the chip and block level.
• Collaborate with CAD/Technology teams and implementation team.
• Lead schedules and support cross-functional engineering efforts.

Skills

Physical Verification

Scripting skills (Perl/Python/Tcl)

Design for Manufacturing

ASIC physical design knowledge

Education

Minimum BS

Tools

Mentor Calibre

Synopsys ICV

Job description

SoC Physical Design Verification Engineer

At Apple, we work every single day to craft products that enrich people's lives! Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining our group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices!In this highly visible role, you will be part of a critical team responsible for physical verification of an SOC.

Description

- As a member of our physical design team, you will perform various types of physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level.- You will collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout.- You will lead schedules and support cross-functional engineering efforts.- You will work on padring, bump, RDL design, and working with the package and floorplan teams.

Minimum Qualifications

• Minimum BS and 3+ years of relevant industry experience.
• Experience with physical verification flows: DRC/LVS/ANT/HVDRC signoff flows and/or full-chip integration methodology.
• Experience with ESD, macro placement design guidelines, digital/analog mixed signal back-end verification checks and/or methodology.

Preferred Qualifications

• Knowledge of all aspects of ASIC physical design and physical verification checks.
• Scripting skills perl/python/tcl to debug flow related issues and automate checks.
• Experience with industry standard tools used for physical verification: Mentor Calibre, and/or Synopsys ICV.
• Tapeout experience with a track record of successful signoff.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .