SoC Design Verification Engineer San Diego, CA

Encore Semi Llc; San Diego (CA); Remote; USD 120,000 - 160,000; Full time

Job summary

A leading company seeks a SoC Design Verification Engineer in San Diego or remote to enhance their design verification processes. This role involves developing testbenches and collaborating with cross-functional teams, requiring deep expertise in RTL verification and automated flows. Candidates with solid experience in System Verilog UVM will excel in this challenging but rewarding position.

Qualifications

• 5+ years experience in RTL Design and Verification with 2+ years in SoC Design Verification.
• Deep knowledge of System Verilog UVM and testbench integration.
• Experience in automated flow development and low-level debug.

Responsibilities

• Testbench development using System Verilog UVM and C.
• Integration of C tests/APIs and SW build flow.
• Coverage collection and closure while collaborating with cross-functional teams.

Skills

System Verilog UVM

RTL Design and Verification

Python Scripting

Low level HW/SW interaction

Multi CPU architectures

AHB, AXI and APB Amba protocols

Tools

Synopsys tools VCS & Verdi

Job description

Job Title: SoC Design Verification Engineer
Locations: San Diego, CA or Remote
Full-Time: Salary + Benefits + Bonuses

Responsibilities:
• Testbench development - System Verilog UVM and C tests
• Integration/development of C tests/APIs and SW build flow
• Integration/development of UVM mailboxes and HW/SW communication components
• Integration of lower level UVM testbenches
• Test plan development
• Power Aware testbench development and simulations
• Seamless porting between simulation/emulation/prototyping platforms
• Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto
• Coverage collection and closure
• Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope

Minimum Qualifications:
• 5+ years of experience in RTL Design and Verification area of which 2+ years of experience in SoC Design Verification and HW/SW verification
• Deep knowledge of System Verilog UVM and vertical testbench integration
• Knowledge of low level HW/SW interaction and debug
• Knowledge of multi CPU and debug architectures
• Knowledge on AHB, AXI and APB Amba protocols
• Experience with development of fully automated flows

Preferred Qualifications:
• Experience with low level SW debug - disasm, Tarmac, trace
• Experience with RISC-V and ARM CPU architectures
• Experience with CoreSight architecture
• Experience with embedded SW low level concepts and debug - Tarmac, ROM, RAM, linkers, elf, disasm, code sections, cache, security
• Experience with coverage merging across simulation and emulation
• Experience with Power Aware and Gate Level Netlist in Emulation
• Experience with development of fully automated flows
• Experience with Gate Level Simulations
• Experience with Synopsys tools VCS & Verdi
• Python Scripting