SOC Physical Design Verification Engineer - Full Time

Rival; Fort Collins, Austin, Portland, Santa Clara (CO, TX, OR, CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Join a leading hardware startup seeking a Silicon PDV Engineer to innovate Risc-V based computing platforms. You'll engage with seasoned engineers, enhance verification methodologies, and ensure high-quality design integration. This dynamic role supports creativity and collaboration within a fast-paced environment.

Qualifications

• Deep understanding of challenges with deep sub-micron nodes.
• Hands-on experience with large hierarchical designs.
• Self-starter and highly motivated.

Responsibilities

• Develop PDV methodology and infrastructure for verification flows.
• Perform full chip integration and physical verification checks.
• Collaborate with design teams for quality deliverables.

Skills

Scripting skills in Tcl

Scripting skills in Python

Problem-solving

Communication

Organization

Education

PhD in Electrical Engineering

Master’s Degree in Electrical Engineering

Bachelor’s Degree in Electrical Engineering

Tools

Siemens Calibre

Job description

Join a cutting-edge and well-funded hardware startup in Silicon Valley as a Silicon PDV Engineer. Our mission is to reimagine silicon and create Risc-V based computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.

Responsibilities

• Develop our PDV methodology and infrastructure to enable the verification flow of large SoCs
• Perform full chip integration and run the complete suite of physical verification checks
• Provide guidance to the implementation teams throughout the project to enable early convergence and final closure
• Interface with various internal and external design teams to ensure the high quality of their deliverables and successful integration
• Work with the package and floorplan teams to define padring and bump map design
• Collaborate with our technology team to define flows and integrate foundry PDK data

Requirements

• Deep understanding of the challenges associated with in deep sub-micron process nodes
• Hands-on experience in closure and tapeout of large hierarchical designs
• Experience with industry standard physical verification tools (Siemens Calibre)
• Strong scripting skills in tcl and python
• Ability and taste for solving complex problems, efficient written and verbal communication, excellent organization skills
• Self starter and highly motivated
• Ability to work cross-functionally with various teams and be productive under aggressive schedules

Education and Experience

• PhD, Master’s Degree or Bachelor’s Degree in EE, EECS or CS.