SoC Physical Design Engineer, STA/Timing

Apple Inc.; Sunnyvale (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

A leading technology company is seeking a SoC Physical Design Engineer specializing in STA/Timing. This role involves collaborating with design teams to enhance timing, creating timing ECOs, and performing deep timing analysis for complex SOCs. Candidates should have a Bachelor's degree and relevant industry experience, with proficiency in Perl and TCL programming.

Qualifications

• Bachelor's degree with 3+ years of relevant industry experience.
• Experience with large design STA and timing closure.
• Proficiency in Perl and TCL programming.

Responsibilities

• Collaborate with design teams to improve timing through logic modifications.
• Create timing ECOs for project tapeouts.
• Perform deep timing path analysis to identify key issues.

Skills

STA

Timing Closure

Perl

TCL

Education

Bachelor's degree

Job description

SoC Physical Design Engineer, STA/Timing

Join Apple as a SoC Physical Design Engineer specializing in STA/Timing. In this role, you will be responsible for the physical implementation of design partitions for complex SOCs using advanced process technology.

Responsibilities

1. Collaborate with design teams to understand constraints and improve timing through logic modifications.
2. Work with the Physical Design team to identify issues and share best practices.
3. Create timing ECOs for project tapeouts.
4. Develop and maintain scripts and methodologies for analysis and runs.
5. Document processes and contribute to guidelines and specifications.
6. Perform deep timing path analysis to identify key issues.
7. Implement timing infrastructure.

Minimum Qualifications

• Bachelor's degree with 3+ years of relevant industry experience.
• Experience with large design STA and timing closure.
• Proficiency in Perl and TCL programming.

Preferred Qualifications

• Hands-on experience in STA.
• Knowledge of timing in high-performance SoC designs in sub-micron technologies.
• Understanding of noise, crosstalk, and OCV effects.
• Experience with circuit modeling, including SPICE.
• Familiarity with ECO techniques.
• Strong communication skills to describe issues clearly and follow through to completion.