Senior Hardware Design Engineer

BayOne Solutions; Palo Alto (CA); On-site; USD 150,000 - 200,000; Full time

Job summary

Join a forward-thinking company as a Sr. Executive in US Recruitments, where your expertise in physical design will be pivotal. You will engage in all design phases of high-performance SoC design, collaborating with various engineering teams to ensure successful tapeout and production silicon. This role offers the chance to lead critical integration activities and apply your extensive knowledge of EDA tools and physical design methodologies. If you're passionate about driving innovation in the semiconductor industry and eager to make a significant impact, this opportunity is for you.

Qualifications

• Extensive experience in physical design at block and full-chip levels.
• Deep knowledge in physical aware synthesis, floorplanning, and routing.

Responsibilities

• Perform place and route, ensuring performance, power, and area requirements.
• Lead full chip SoC integration activities and define EM-IR signoff requirements.

Skills

Physical Design

EDA Tools (Synopsys/Cadence)

Scripting (Perl/Tcl)

SoC Architecture

Timing Analysis

Power Analysis

Physical Verification (DRC/LVS)

Tools

Redhawk

Redhawk-SC

Job description

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Sr. Executive - US Recruitments at BayOne Solutions

As a Sr. physical design engineer, you will contribute to all design phases of physical design of high performance SoC design at both the block and subchip levels, as well as the full-chip level from RTL to GDSII. You will collaborate with the Foundry Process Engineer, SoC Architect, Microarchitecture, Packaging, Signal Integrity and Power Integrity teams to drive the overall Physical Design aspects, leading to a successful tapeout and production silicon.

Key Qualifications include (but not limited to):

• Extensive physical design experiences at both the block level and subchip level, as well as full-chip level is a plus.
• Deep knowledge in physical design, including physical aware synthesis, floorplanning, clock tree implementation, routing, STA timing signoff, and chip-finishing.
• Good knowledge of basic SoC architecture. Be able to work with Front-end design team to address timing, congestion and power issues.
• In-Depth Knowledge of design flow from RTL to GDSII.
• Good knowledge of EM-IR sign-off requirements.
• Experience in using EDA tools like Synopsys (/Cadence) for PPA optimization.
• Good script skills such as perl/tcl.

Responsibilities include (but not limited to):

• Perform subchip level and block level place and route, and close design to meeting performance, power and area.
• Lead and Perform all aspects of full chip SoC integration activities: die size optimization, floorplanning, hard IP integration, partitioning, chip level clock planning, bump placement / RDL routing, power grid generation, full chip STA timing, DFT strategy planning, and final physical verification.
• Good knowledge of timing analysis, power analysis, physical verification (DRC/LVS), and formal verification.
• Working knowledge of UPF specification in Power Intent design, implementation, and verification of power gating, level shifter, and isolation.
• Define EM-IR signoff requirements and sign-off methodology.
• Define and support Static and Dynamic, thermal, electro-migration, peak current, di/dt, and effective resistance analysis.
• Be an EM-IR sign-off lead with successful tape out track records.
• Excellent hand-on experience in voltage drop analysis using redhawk or redhawk-SC.
• Excellent hand-on experience and debugging skills of finding root cause of voltage drop and EM issues.
• Solid background in EM-IR fundamentals, analytical aptitude and excellent attention to detail.

Seniority level

Mid-Senior level

Employment type

Contract

Job function

Analyst, Engineering, and Information Technology

Industries

Motor Vehicle Manufacturing, Retail Motor Vehicles, and Motor Vehicle Parts Manufacturing