Senior Staff Physical Design Engineer - Static Timing Analysis

Marvell Technology; Santa Clara (CA); On-site; USD 124,000 - 187,000; Full time

Job summary

Marvell Technology is seeking a Senior Staff Physical Design Engineer specializing in Static Timing Analysis to enhance their Central Data Center Engineering team. The role involves leading the timing closure of ASIC designs and optimizing methodologies, requiring advanced skills in EDA tools and teamwork in a cutting-edge tech environment.

Benefits

Flexible time off

401k

Paid time off to volunteer

Year-end shutdown

Floating holidays

Comprehensive health and financial benefits

Qualifications

• 8+ years of experience in STA and timing closure for ASIC designs.
• Proficiency with EDA tools and good understanding of timing methodologies.
• Experience collaborating with cross-functional teams.

Responsibilities

• Perform full-chip and block-level static timing analysis for ASIC designs.
• Own timing closure across RTL, synthesis, and physical implementation.
• Provide guidance on design partitioning and timing strategies.

Skills

Static Timing Analysis

Problem Solving

Attention to Detail

Communication

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related discipline

Tools

Synopsys PrimeTime

Cadence Tempus

Tcl

Perl

Python

Job description

Senior Staff Physical Design Engineer - Static Timing Analysis

Join to apply for the Senior Staff Physical Design Engineer - Static Timing Analysis role at Marvell Technology

Senior Staff Physical Design Engineer - Static Timing Analysis

2 days ago Be among the first 25 applicants

Join to apply for the Senior Staff Physical Design Engineer - Static Timing Analysis role at Marvell Technology

Get AI-powered advice on this job and more exclusive features.

Direct message the job poster from Marvell Technology

Proven Senior Recruiter/Leader| Helping Companies Translate Their Business Goals to Reality

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

At Marvell, we build semiconductor solutions that move, store, process, and secure the world’s data. As part of our Central Data Center Engineering team, you’ll help shape the future of compute infrastructure by developing high-performance ASICs that power next-generation data centers. We’re looking for passionate engineers who thrive in a collaborative and innovative environment.

We are seeking a Senior Staff Physical Design Engineer – Static Timing Analysis (STA) to join our growing team. In this role, you will be responsible for timing closure of large, complex ASIC designs from RTL to final signoff. You will work closely with cross-functional teams including RTL design, synthesis, and physical implementation to ensure on-time and high-quality tape-outs.

What You Can Expect

• Perform full-chip and block-level static timing analysis for advanced ASIC designs
• Develop, maintain, and optimize timing constraints, methodologies, and automation scripts
• Own timing closure across all stages of the design flow: RTL, synthesis, physical implementation, and signoff
• Debug and resolve complex timing violations and drive design fixes
• Collaborate closely with design, synthesis, and physical design teams to meet performance, power, and area (PPA) goals
• Provide guidance on design partitioning, floorplanning, and timing budgeting strategies
• Contribute to design reviews and provide expert insights for design improvements
  
  

What We're Looking For

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline
• 8+ years of hands-on experience in STA and timing closure for large-scale ASIC designs
• Strong proficiency with EDA tools such as Synopsys PrimeTime, PrimeTime SI, and/or Cadence Tempus
• Deep understanding of timing concepts, constraints development, and signoff methodologies
• Demonstrated success in driving complex designs to timing closure
• Excellent problem-solving skills and strong attention to detail
• Strong communication skills and proven ability to work effectively in a collaborative team environment
• Preferred Experience:
• Familiarity with scripting languages such as Tcl, Perl, or Python
• Experience with hierarchical timing and multi-mode/multi-corner (MMMC) analysis
• Knowledge of data center ASIC architecture or high-performance computing systems
  
  

Expected Base Pay Range (USD)

124,420 - 186,400, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation And Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at [e-mail].

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering and Information Technology

• Industries

  Semiconductor Manufacturing

Referrals increase your chances of interviewing at Marvell Technology by 2x

Sign in to set job alerts for “Senior Physical Design Engineer” roles.

Senior Mechanical Engineer – Interconnect Design

Senior Quality Engineer (Design Control & Risk Management)

Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team

Sr. ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team

Santa Clara, CA $136,000.00-$310,500.00 4 days ago

Sunnyvale, CA $173,000.00-$249,000.00 5 days ago

SoC Physical Design Engineer, Implementation

Physical Design Engineer, Custom Datapath

Sunnyvale, CA $175,800.00-$312,200.00 2 days ago

Sr. Physical Design Engineer, Annapurna Labs

San Jose, CA $165,700.00-$232,900.00 2 weeks ago

Physical Design Engineer, Static Timing Analysis

San Jose, CA $120,000.00-$200,000.00 2 weeks ago

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

Sunnyvale, CA $170,000.00-$230,000.00 1 week ago

Physical Design Engineer, Static Timing Analysis, Google Cloud

Senior ASIC Physical Design Engineer - High Performance Designs

Santa Clara, CA $136,000.00-$264,500.00 5 days ago

Senior Physical Design Methodology Engineer

We’re unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI.