SoC Performance Architect: Power & NoC Modeling Lead

QUALCOMM, Inc.; Santa Clara (CA); On-site; USD 273,000 - 409,000; Full time

Job summary

Qualcomm Technologies, Inc. seeks a SoC Performance Architect to create performance and power models for fabric NoC, DRAM controllers and IO blocks for server-class SoCs, correlating models against RTL behavior and prototyping ideas for productizing perf/power features.

The role involves RTL verification planning, developing robust models, and collaborating with RTL and architecture teams to drive design improvements toward silicon success.

Qualifications

• Bachelor's degree in Electrical Engineering, CS, or related field with 8+ years of Systems Engineering or related work.
• Master's degree in Electrical Engineering, CS, or related field with 7+ years of experience.
• PhD in Electrical Engineering, CS, or related field with 6+ years of experience.
• 2+ years of experience in one or more system architecture technology areas and products.

Responsibilities

• Conduct RTL performance verification with test plans and checkers.
• Develop SoC performance/power models for NoCs, caches, memory/IO controllers.
• Verify model correctness with unit tests and debugging mismatches.
• Prototype and characterize performance/power improvements.
• Collaborate with architects and RTL to productize improvements.

Skills

SoC performance/power modeling

Computer architecture fundamentals

C++

Python/Perl

Performance analysis and debugging

Troubleshoot performance problems

Education

Bachelor's degree in Electrical Engineering, Computer Science, or related field

Master's degree in Electrical Engineering, Computer Science, or related field

PhD in Electrical Engineering, Computer Science, or related field

Tools

Python

Perl

Job description

Qualcomm Technologies, Inc. seeks a SoC Performance Architect to create performance and power models for fabric NoC, DRAM controllers and IO blocks for server-class SoCs, correlating models against RTL behavior and prototyping ideas for productizing perf/power features.

The role involves RTL verification planning, developing robust models, and collaborating with RTL and architecture teams to drive design improvements toward silicon success.