Senior SoC Performance Architect: NoC & Power Modeling

Qualcomm Incorporated; Santa Clara (CA); On-site; USD 273,000 - 409,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking an experienced SoC Performance Architect to create performance and power models for NoC/DRAM/IO blocks in server-class SoCs. You will correlate models with RTL, prototype performance ideas, and help productize features for future SoC designs.

The role requires deep CPU/SoC modeling expertise, strong C++/Python/Perl scripting, and ability to troubleshoot performance issues across RTL and models. Location flexibility includes multiple US sites.

Qualifications

• Bachelor's degree and 8+ years of Systems Engineering or related work experience.
• Master's degree and 7+ years of Systems Engineering or related work experience.
• PhD and 6+ years of Systems Engineering or related work experience.
• 2+ years of experience in one or more system architecture technology areas and products (e.g., Power System, Shared Resource Management, Limits/Thermal Management, Hardware Islands).

Responsibilities

• Conduct RTL performance verification with verification plans and directed tests/checkers.
• Develop a SoC performance/power model for blocks such as interconnect NoCs, distributed system caches, memory controllers, IO controllers.
• Verify model correctness by unit tests and debugging mismatches against expectations.
• Identify ideas to improve SoC performance/power; prototype and characterize them in the model.
• Collaborate with architects and RTL developers to productize improvements from studies.

Skills

SoC performance/power modeling

Interconnects & QoS

RTL debugging & performance analysis

C++

Python/Perl scripting

Education

Bachelor's degree in Electrical Engineering or Computer Science

Master's degree in Electrical Engineering or Computer Science

PhD in Electrical Engineering or Computer Science

Tools

C++

Python

Perl

Job description

Qualcomm Technologies, Inc. is seeking an experienced SoC Performance Architect to create performance and power models for NoC/DRAM/IO blocks in server-class SoCs. You will correlate models with RTL, prototype performance ideas, and help productize features for future SoC designs.

The role requires deep CPU/SoC modeling expertise, strong C++/Python/Perl scripting, and ability to troubleshoot performance issues across RTL and models. Location flexibility includes multiple US sites.