SoC Management Architect: Lead AI Acceleration Platform

Majestic Labs ai; Los Altos (CA); On-site; USD 180,000 - 250,000; Full time

Job summary

Majestic Labs ai is seeking a seasoned SoC Architect to lead management subsystem design for its AI acceleration platform. You will define architecture, integrate ARM cores, PCIe, and memory interfaces, and work across hardware, firmware, and system teams in a fast-paced startup.

You will drive control path design, interconnect fabrics, and debug infrastructures, ensuring high performance with optimal power and area across the SoC. Strong leadership and collaboration are essential.

Qualifications

• Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or related field.
• 6+ years of experience in SoC architecture and design, with emphasis on management or control subsystems.
• Proven experience with ARM core integration, PCIe, DDR/LPDDR, and peripheral interfaces (SPI, I2C, UART).
• Strong understanding of SoC design flows, memory hierarchy, and interconnect fabrics.
• Hands‑on experience in control path design, driver interfaces, and interrupt management.

Responsibilities

• Define and own the management subsystem architecture for Majestic’s AI SoC.
• Integrate ARM cores (CSS / Cortex-A) and associated subsystems for control, configuration, and monitoring.
• Architect PCIe connectivity and high-bandwidth IO to ensure robust host and device communication.
• Specify and integrate DDR/LPDDR interfaces and memory management structures.
• Design peripheral and control interfaces, including SPI, I2C, UART, GPIO, and system control buses.
• Develop scheduler and interrupt schemes, driver-facing control paths, and configuration frameworks.
• Integrate and optimize debug and trace infrastructures (CoreSight, profilers, diagnostic tools).
• Collaborate with RTL, verification, firmware, and board teams to ensure seamless hardware-software co-design.
• Drive tradeoffs and decisions to achieve performance, power, and area targets across the SoC.

Skills

ARM core integration

PCIe

DDR/LPDDR

SPI

I2C

UART

SoC architecture

interconnect fabrics

memory hierarchy

driver interfaces

interrupt management

leadership

cross-functional collaboration

Education

Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or related field

Tools

CoreSight

FPGA-based validation

Job description

Majestic Labs ai is seeking a seasoned SoC Architect to lead management subsystem design for its AI acceleration platform. You will define architecture, integrate ARM cores, PCIe, and memory interfaces, and work across hardware, firmware, and system teams in a fast-paced startup.

You will drive control path design, interconnect fabrics, and debug infrastructures, ensuring high performance with optimal power and area across the SoC. Strong leadership and collaboration are essential.