SOC Architect

OpenAI; San Francisco (CA); On-site; USD 150,000 - 200,000; Full time

Job summary

OpenAI is seeking an experienced SoC Architect in San Francisco to lead the development of custom AI silicon for edge deployments. The role involves defining SoC architecture, driving tradeoff analysis, and collaborating with both internal teams and external partners. Ideal candidates will have a strong background in SoC/ASIC architecture, AI/ML, and energy-efficient design. This is an opportunity to shape next-generation silicon solutions in a fast-paced environment.

Qualifications

• Proven experience defining and delivering complex SoC or ASIC architectures from concept to production.
• Deep understanding of AI/ML accelerators and edge inference workloads.
• Strong knowledge of SoC subsystems including CPU/GPU/NPU architectures.

Responsibilities

• Define the architecture and technical roadmap for custom SoCs.
• Drive system-level tradeoff analysis across compute, memory, and power constraints.
• Collaborate with internal and external teams to align architecture with platform needs.

Skills

SoC or ASIC architecture

AI/ML accelerators

energy-efficient compute design

cross-functional collaboration

communication skills

Job description

About the Role

We are seeking an experienced SoC Architect to lead the definition and development of next-generation custom AI silicon for edge deployments. This role will be responsible for shaping the architecture of highly efficient, high-performance SoCs optimized for machine learning inference and on-device intelligence. You will work cross-functionally with internal engineering teams and external ecosystem partners to translate product requirements into scalable silicon solutions, driving execution from concept through delivery.

In this role you will:

• Define the architecture and technical roadmap for custom SoCs targeted for edge applications.
• Drive system-level tradeoff analysis across compute, memory, interconnect, power, thermal, and cost constraints.
• Architect energy-efficient ML compute subsystems optimized for inference workloads and real-world deployment environments.
• Collaborate with internal hardware, software, systems, and product teams to align architecture with platform needs.
• Partner with external silicon vendors, IP providers, and manufacturing partners to execute development plans.
• Lead hardware/software co-design efforts to maximize performance per watt and end-to-end system efficiency.
• Guide implementation teams through microarchitecture, RTL development, validation, and bring-up phases.
• Operate effectively in agile development environments and help teams deliver against aggressive schedules and milestones.

You might thrive in this role if:

• Proven experience defining and delivering complex SoC or ASIC architectures from concept to production.
• Deep understanding of AI/ML accelerators, edge inference workloads, and energy-efficient compute design.
• Strong knowledge of SoC subsystems including CPU/GPU/NPU architectures, memory hierarchies, interconnects, and power management.
• Experience working with both internal engineering organizations and external strategic partners.
• Ability to lead cross-functional teams in fast-paced, execution-driven environments.
• Strong communication skills with the ability to influence technical direction across organizations.

Preferred Qualifications

• Experience with edge AI devices, embedded systems, or consumer hardware platforms.
• Background in performance modeling, silicon cost optimization, and workload-driven architecture.
• Familiarity with advanced process nodes and modern semiconductor development flows.

We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic.