SoC Management Subsystem Architect

Majestic Labs ai; Los Altos (CA); On-site; USD 180,000 - 250,000; Full time

Job summary

Majestic Labs ai is seeking a seasoned SoC Architect to lead management subsystem design for its AI acceleration platform. You will define architecture, integrate ARM cores, PCIe, and memory interfaces, and work across hardware, firmware, and system teams in a fast-paced startup.

You will drive control path design, interconnect fabrics, and debug infrastructures, ensuring high performance with optimal power and area across the SoC. Strong leadership and collaboration are essential.

Qualifications

• Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or related field.
• 6+ years of experience in SoC architecture and design, with emphasis on management or control subsystems.
• Proven experience with ARM core integration, PCIe, DDR/LPDDR, and peripheral interfaces (SPI, I2C, UART).
• Strong understanding of SoC design flows, memory hierarchy, and interconnect fabrics.
• Hands‑on experience in control path design, driver interfaces, and interrupt management.

Responsibilities

• Define and own the management subsystem architecture for Majestic’s AI SoC.
• Integrate ARM cores (CSS / Cortex-A) and associated subsystems for control, configuration, and monitoring.
• Architect PCIe connectivity and high-bandwidth IO to ensure robust host and device communication.
• Specify and integrate DDR/LPDDR interfaces and memory management structures.
• Design peripheral and control interfaces, including SPI, I2C, UART, GPIO, and system control buses.
• Develop scheduler and interrupt schemes, driver-facing control paths, and configuration frameworks.
• Integrate and optimize debug and trace infrastructures (CoreSight, profilers, diagnostic tools).
• Collaborate with RTL, verification, firmware, and board teams to ensure seamless hardware-software co-design.
• Drive tradeoffs and decisions to achieve performance, power, and area targets across the SoC.

Skills

ARM core integration

PCIe

DDR/LPDDR

SPI

I2C

UART

SoC architecture

interconnect fabrics

memory hierarchy

driver interfaces

interrupt management

leadership

cross-functional collaboration

Education

Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or related field

Tools

CoreSight

FPGA-based validation

Job description

About Majestic Labs

We’re a fast-moving, US-Israeli AI startup building next-generation infrastructure for the world’s most demanding AI workloads. Our mission is to accelerate the future of intelligence and make it ubiquitously accessible by delivering full stack custom AI servers optimized for large-scale inference and training. Backed by top-tier investors and led by industry veterans, we’re scaling rapidly. We seek forward-thinking engineers and operators who thrive in a collaborative environment and excel at solving complex challenges from first principles. If you want to build infrastructure that fundamentally changes what the world can accomplish with AI, come join us!

About The Position

We are looking for a seasoned SoC Architect to lead the design and integration of the management subsystem within Majestic’s AI acceleration platform. In this role, you will define and drive SoC-level architecture for control and management flows - integrating ARM cores, interconnects, high-speed IO, and system management interfaces. You’ll collaborate closely with peer architects, hardware, firmware, and system engineers to ensure a cohesive, high-performance design that bridges silicon and software seamlessly. This is a hands‑on architecture role that combines technical depth, system-level thinking, and cross-domain leadership in a fast-moving startup environment.

Responsibilities

• Define and own the management subsystem architecture for Majestic’s AI SoC.
• Integrate ARM cores (CSS / Cortex-A) and associated subsystems for control, configuration, and monitoring.
• Architect PCIe connectivity and high-bandwidth IO to ensure robust host and device communication.
• Specify and integrate DDR/LPDDR interfaces and memory management structures.
• Design peripheral and control interfaces, including SPI, I2C, UART, GPIO, and system control buses.
• Develop scheduler and interrupt schemes, driver-facing control paths, and configuration frameworks.
• Integrate and optimize debug and trace infrastructures (CoreSight, profilers, diagnostic tools).
• Collaborate with RTL, verification, firmware, and board teams to ensure seamless hardware-software co-design.
• Drive tradeoffs and decisions to achieve performance, power, and area targets across the SoC.

Requirements

• Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or related field.
• 6+ years of experience in SoC architecture and design, with emphasis on management or control subsystems.
• Proven experience with ARM core integration, PCIe, DDR/LPDDR, and peripheral interfaces (SPI, I2C, UART).
• Strong understanding of SoC design flows, memory hierarchy, and interconnect fabrics.
• Hands‑on experience in control path design, driver interfaces, and interrupt management.
• Solid communication and teamwork skills, with the ability to lead cross-functional architectural discussions.

Preferred Qualifications

• Experience with AI/ML acceleration hardware or high-performance compute SoCs.
• Knowledge of board-level integration and hardware-software co-validation.
• Familiarity with silicon prototyping, emulation, or FPGA-based validation.
• Expertise in low-power design and high-bandwidth interconnect architectures.
• Deep experience with debug tools (CoreSight, trace analyzers, profilers) and performance instrumentation.

We seek smart, curious, self-driven individuals who enjoy creative problem-solving and continuous learning. Even if you don't meet all requirements, we'd love to hear from you if you have the mindset to tackle complex challenges. Majestic Labs is an equal opportunity employer deeply committed to diversity of background and thought. If you are ready to dare greatly, learn from mistakes, engage in vigorous debates, and help create a step‑function shift in human technical capability, we want to meet you!