SoC Design Verification Engineer

Encore Semi Llc; San Diego (CA); Hybrid; USD 90,000 - 150,000; Full time

Job summary

An established industry player is seeking a SoC Design Verification Engineer to join their innovative team. In this role, you will develop and integrate testbenches, ensuring seamless communication between hardware and software components. Your expertise in System Verilog UVM and RTL design will be crucial as you collaborate with cross-functional teams to enhance verification processes. This position offers a unique opportunity to work on cutting-edge technologies in a dynamic environment, where your contributions will significantly impact product development. If you are passionate about advancing SoC design verification and thrive in a collaborative setting, this role is perfect for you.

Qualifications

• 5+ years of experience in RTL Design and Verification.
• Deep knowledge of System Verilog UVM and testbench integration.
• Experience with automated flows and multi CPU architectures.

Responsibilities

• Develop testbenches using System Verilog UVM and C.
• Integrate and develop tests/APIs for HW/SW communication.
• Work with cross-functional teams to identify coverage scope.

Skills

System Verilog UVM

C programming

RTL Design

SoC Design Verification

HW/SW verification

AHB, AXI, APB Amba protocols

Python Scripting

Tools

Synopsys VCS

Synopsys Verdi

Job description

Job Title: SoC Design Verification Engineer
Locations: San Diego, CA or Remote
Full-Time: Salary + Benefits + Bonuses

Responsibilities:
• Testbench development - System Verilog UVM and C tests
• Integration/development of C tests/APIs and SW build flow
• Integration/development of UVM mailboxes and HW/SW communication components
• Integration of lower level UVM testbenches
• Test plan development
• Power Aware testbench development and simulations
• Seamless porting between simulation/emulation/prototyping platforms
• Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto
• Coverage collection and closure
• Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope

Minimum Qualifications:
• 5+ years of experience in RTL Design and Verification area of which 2+ years of experience in SoC Design Verification and HW/SW verification
• Deep knowledge of System Verilog UVM and vertical testbench integration
• Knowledge of low level HW/SW interaction and debug
• Knowledge of multi CPU and debug architectures
• Knowledge on AHB, AXI and APB Amba protocols
• Experience with development of fully automated flows

Preferred Qualifications:
• Experience with low level SW debug - disasm, Tarmac, trace
• Experience with RISC-V and ARM CPU architectures
• Experience with CoreSight architecture
• Experience with embedded SW low level concepts and debug - Tarmac, ROM, RAM, linkers, elf, disasm, code sections, cache, security
• Experience with coverage merging across simulation and emulation
• Experience with Power Aware and Gate Level Netlist in Emulation
• Experience with development of fully automated flows
• Experience with Gate Level Simulations
• Experience with Synopsys tools VCS & Verdi
• Python Scripting