GSoC Design Verification Engineer

Socket.dev; San Diego (CA); On-site; USD 99,000 - 148,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking highly motivated new college graduates and experienced Design Verification Engineers to join the GSoC Design Verification team.

You will verify next-generation Data Center SoCs powering AI, high-performance computing, mobile, and cloud infrastructure products. This role offers collaboration with architects, design engineers, software teams, and verification specialists to build scalable verification solutions, drive verification closure, and support

Qualifications

• Bachelor's or master's degree in electrical engineering, computer engineering, computer science, or related field.
• Strong knowledge of SystemVerilog, UVM, C, SVA, coverage-driven verification.
• Experience developing verification environments from architecture/specification through signoff.
• Strong understanding of computer architecture and digital design fundamentals.
• Experience debugging complex SoC-level issues.
• Proficiency in Python or scripting languages for automation.

Responsibilities

• Develop and execute verification plans for SoC, subsystem, and IP-level features.
• Design and implement scalable SystemVerilog/UVM-based verification environments.
• Create directed and constrained-random test scenarios to validate functionality and architecture use cases.
• Develop assertions, functional coverage models, and checkers.
• Debug RTL, testbench, and integration issues with design teams to resolve defects.
• Drive coverage closure using functional and code coverage metrics.
• Participate in architecture and design reviews to ensure verification requirements are incorporated early.

Skills

SystemVerilog

UVM

C

SVA

Python

AI-assisted verification

Verilog

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Veloce Emulation

Formal Verification

Assertion-Based Verification (SVA)

Job description

Company

Qualcomm Technologies, Inc.

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

Qualcomm is a company of inventors whosebreakthroughinnovationsare accelerating progressin data center technologies, connectivity, and new possibilities thatare transformingindustries,creating opportunities, andenrichinglives.Bringing this potential to life requiresinventive minds with diverse skills, backgrounds, andperspectives to developworld-changing technologies and products. This is the Invention Age—and this is where youcan make an impact.

Job Overview

We arelooking forhighly motivated new college graduates and experienced Design Verification Engineers to join ourGSoCDesign Verification team. In this role, you willverifynext-generation Data Center SoCs that power AI, high-performance computing, mobile, and cloud infrastructure products. You willpartnerclosely with architects, design engineers, software teams, and verification specialists tobuildscalable verification solutions, drive verification closure, andsupportfirst-silicon success for complex SoC designs.

Thisroleprovidesthe opportunity to work onadvancedtechnologiessuch asmulti-core CPUs, cache coherency systems, memory subsystems, AI/ML accelerators, high-speed interconnects, security, andmodernSoCarchitecture.

As an SOC Verification Engineer, you willbe responsible forensuring the quality and functionality of System-on-Chip (SOC) designs through comprehensive verification processes. You will develop and implement verification methodologies, create test plans, and execute verification tests toidentifyand resolve design issues.Additionallyin this role,you willalsohelpbuildthe AI-powered intelligent agents thatassistengineers in areas such as Design Verification, regression management, debug automation, test planning, and design analysis.

Key Responsibilities

• Develop and execute comprehensive verification plans for SoC, subsystem, and IP-level features.
• Design and implement scalable System Verilog/UVM-based and Processor-based verification environments.
• Create directed and constrained-random test scenarios to validate functionality and architectural use cases.
• Develop assertions, functional coverage models, and checkers.
• Debug RTL, testbench, and integration issues and work closely with design teams to resolve defects.
• Drive coverage closure using functional and code coverage metrics.
• Participate in architecture and design reviews to ensure verification requirements are incorporated early in the development cycle.
• Verify complex Data Center SoC features.
• Support emulation and acceleration-based verification whenrequired.
• Contribute tomethodologyimprovements, automation, reusable verification components, and AI-assisted verification flows.
• Develop AI agents that automate engineering tasks acrossdomainsworkflows.
• Build agent workflows using modern LLM frameworks and agent orchestration platforms.
• Create integrations between AI systems and engineering tools, databases, and knowledge repositories.
• Develop Retrieval Augmented Generation (RAG) pipelines forsystemdocumentation, specifications, and engineering knowledge.

Qualifications

• Bachelor's or master's degree in electrical engineering, Computer Engineering, Computer Science, or related field.
• Strong knowledge of: System Verilog, UVM, C, Assertion-Based Verification (SVA), Coverage-Driven Verification, System level Use case verification
• Experience developing verification environments from architecture/specification through signoff.
• Strong understanding of computer architecture and digital design fundamentals.
• Experience debugging complex SoC-level issues.
• Strong problem-solving and analytical skills.
• Proficiencyin Python or scripting languages for automation.
• AI-assisted verification of workflows and test generation.
• Excellent communication and collaboration skills.

Preferred Qualifications

• Experience in full-chip or subsystem verification environments.
• Experience with one or more of the following:
• CPU verification
• Cache coherency protocols (ACE, CHI, CXL)
• DDR or HBM memory systems
• PCIe, Ethernet, or networking protocols
• AI/ML acceleratordesignverification
• Security and RAS feature verification
• SystemPower andPerformance verification
• Experience with: Portable Stimulus (PSS),Formal Verification,Emulation platforms (Veloce/Palladium/ZeBu),Power-aware verification
• Understanding of machine learning and Generative AI concepts.
• Knowledge of LLMs such as GPT, Claude, Llama, or equivalent models.
• Collaborate with RTL, DV, CAD, and AI platform teams toidentifyautomation opportunities.
• Measure and track productivity improvements delivered through AI-enabled workflows.
• Contribute to internal AI platforms, reusable skills, tools, and agent libraries.

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field.

Pay range and Other Compensation & Benefits

$98,500.00 - $147,700.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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