SOC Engineering, Principal Engineer

Synopsys, Inc.; Austin (TX); On-site; USD 180,000 - 240,000; Full time

Job summary

Synopsys, Inc. is seeking a hands-on verification leader to translate complex architectural requirements into executable verification plans and measurable sign-off criteria.

You will architect SystemVerilog/UVM environments and guide engineers through coverage closure and sign-off across full-chip engagements. You will collaborate directly with customers and cross-functional teams, driving risk-based decisions and ensuring traceable verification evidence.

Qualifications

• 15+ years of ASIC/SoC design verification experience.
• Strong SystemVerilog/UVM expertise with constrained-random stimulus and coverage.
• Experience leading verification teams through milestones and sign-off.
• Hands-on verification of clock, reset, and power-control logic.
• Experience with AMBA interfaces and coherent interconnect protocols.

Responsibilities

• Lead subsystem and SoC verification from planning to sign-off.
• Translate specs into verification plans, test scenarios, and coverage models.
• Architect reusable SystemVerilog/UVM environments with VIPs and models.
• Verify processor/system integration including boot, memory, and interrupts.
• Mentor engineers and coordinate execution across architecture, RTL, firmware, and QA teams.
• Own regression health, defect tracking, and sign-off evidence.

Skills

ASIC/SoC verification leadership

SystemVerilog/UVM

Regression management

Coverage analysis

Embedded C/C++

Multicore/SoC architecture

AMBA/coherent interconnects

Debug/fault management

Cross-functional communication

Education

Bachelor's or Master’s in Electrical or Computer Engineering

Tools

Synopsys VCS

Verdi

VC Formal

Python scripting

Tcl

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You are a hands-on verification leader who translates complex architectural and system requirements into executable verification plans and measurable sign-off criteria. You understand that the hardest integration bugs often emerge from interactions between processors, interconnects, memory, firmware, and system-control logic.

You combine technical leadership with practical execution. You can architect a UVM environment, debug a processor boot failure, investigate an interrupt or power-sequencing issue, and guide engineers through coverage closure. You distinguish RTL defects from testbench, software, configuration, and specification issues, and drive them toward resolution.

You lead with clear priorities and technical credibility. You work directly with customers and cross-functional teams, communicate risks early, and make evidence-based readiness decisions. Your architectural understanding and reusable verification skills allow you to contribute across different subsystem functions and full-chip engagements.

What You’ll Be Doing

• Lead subsystem and SoC verification from requirements review and planning through environment development, regression execution, coverage closure, and sign-off.
• Translate specifications into verification plans, test scenarios, coverage models, checkers, and traceable acceptance criteria.
• Architect reusable SystemVerilog/UVM environments integrating commercial VIP, processor models, register models, assertions, reference models, and scoreboards.
• Verify processor and system integration, including boot flows, address mapping, memory access, coherency, interrupts, timers, debug, and configuration interfaces.
• Drive verification of clock switching and gating, reset sequencing, power-state transitions, isolation, retention, and cross-domain dependencies.
• Verify fault-management and recovery behavior, including error capture, masking, aggregation, ECC/parity, watchdogs, monitors, and error injection.
• Develop directed, constrained-random, and embedded C tests covering concurrent traffic, corner cases, initialization, and failure/recovery sequences.
• Lead root-cause debug across RTL, verification environments, firmware, and third-party IP; coordinate fixes and verify resolution.
• Own regression health, defect tracking, requirements traceability, functional/code coverage, milestone readiness, and sign-off evidence.
• Mentor engineers and coordinate technical execution with architecture, design, firmware, formal verification, and other engineering teams.

The Impact You Will Have

• Identify critical integration and system-level defects before silicon, improving quality and reducing late-stage program risk.
• Establish clear verification scope and measurable closure criteria that support predictable customer milestones.
• Build reusable environments and methodologies that accelerate future subsystem and SoC engagements.
• Improve execution efficiency through effective debug, automation, disciplined regressions, and risk-based prioritization.
• Strengthen customer confidence through transparent communication and traceable verification evidence.
• Develop engineers into independent technical owners and future verification leaders.

What You’ll Need

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.
• 15+ years of ASIC/SoC design verification experience, including hands-on subsystem or full-chip ownership through multiple tape-outs.
• Proven experience leading verification teams and driving technical execution through major milestones and sign-off.
• Strong SystemVerilog/UVM expertise, including constrained-random stimulus, assertions, functional coverage, scoreboards, and register models.
• Deep understanding of processor-based SoC architectures, including multicore integration, memory hierarchy, coherent interconnects, interrupts, boot, and debug.
• Hands-on experience verifying clock, reset, and power-control logic, including sequencing, state transitions, dependencies, and recovery behavior.
• Experience verifying hardware fault-management mechanisms, including error reporting, masking, ECC/parity, error injection, and fault recovery.
• Working knowledge of AMBA interfaces and coherent interconnect protocols, with practical system-level transaction-debug experience.
• Embedded C/C++ experience for initialization, processor-driven tests, interrupt handling, and hardware/software debug.
• Strong capability in regression management, coverage analysis, requirements traceability, and verification closure.
• Experience with simulation, waveform-debug, and verification-management tools, plus scripting in Python, Tcl, or shell.
• Strong communication skills and experience working with customers and geographically distributed teams.

Preferred Qualifications

• Low-power verification using UPF and power-aware simulation.
• Lockstep verification and requirements-based verification for safety-critical designs.
• Formal verification and assertion-based verification experience.
• Emulation experience, including platform bring-up, software-driven testing, or simulation-to-emulation test reuse, is a plus.
• Experience with Synopsys VCS, Verdi, VC Formal, and verification-management tools.

Who You Are

• You identify missing scenarios in a verification plan and explain the resulting product risk.
• You move comfortably between technical planning, environment reviews, and hands-on debug.
• You challenge ambiguous requirements constructively and establish agreement on expected behavior.
• You give engineers clear ownership while remaining accountable for integration and delivery.
• You assess readiness using passing tests, coverage, and defect evidence rather than activity alone.
• You make sound sign-off recommendations under schedule pressure and communicate unresolved risks clearly.

The Team You’ll Be Part Of

You will join the Synopsys Solutions group, delivering end-to-end SoC and subsystem engineering services across diverse customer programs. You will collaborate with architecture, RTL design, firmware, verification, DFT, and physical design teams. Your responsibilities may span different subsystem functions and full-chip engagements, providing opportunities to apply your technical leadership across architectures and markets.