SoC Design Lead Engineer ARM MultiCore Data Center

ScaleFlux, Inc.; Milpitas (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

ScaleFlux, Inc. seeks a SoC Design Lead Engineer to spearhead a high-performance ARM-based multi-core SOC project for data-center infrastructure. You will drive architecture, RTL design, and IP integration within a fast-paced, results-driven team.

The role collaborates with verification, emulation, and prototype groups to deliver low-power, high-performance solutions, requiring strong leadership and cross‑functional communication to coordinate multiple IP vendors and internal teams.

Qualifications

• BE/BS in Electrical/Electronic Engineering or VLSI with 10+ years of practical experience.
• Expertise in ARM v8 and v9 specifications and their impact to SoC system architecture.
• Exposure to ARM platform architecture specifications and AMBA bus protocols.
• Strong experience with Verilog/SystemVerilog and RTL level checks; knowledge of low power tech is a plus.
• Ability to lead design teams and coordinate multiple IP vendors.

Responsibilities

• Contribute to SoC architecture for a multi-core ARM SOC.
• Define SoC micro architecture and design.
• Build SoC around ARM subsystem components and other IPs; design clock-reset architecture and RTL implementation.
• Integration of all IPs into SoC and collaboration with verification for complete SoC verification.
• RTL simulation, debug, and support emulation, FPGA, and prototyping efforts.

Skills

ARM v8/v9 architecture

ARM ecosystem components

AMBA bus protocols

SystemVerilog/Verilog

RTL development & checks

IP integration & interconnects

IP vendors coordination

leadership & communication

low power methodology knowledge

Education

BE/BS in Electrical/Electronic Engineering/VLSI

Tools

Verilog

SystemVerilog

RTL checks

Job description

ScaleFlux, Inc. seeks a SoC Design Lead Engineer to spearhead a high-performance ARM-based multi-core SOC project for data-center infrastructure. You will drive architecture, RTL design, and IP integration within a fast-paced, results-driven team.

The role collaborates with verification, emulation, and prototype groups to deliver low-power, high-performance solutions, requiring strong leadership and cross‑functional communication to coordinate multiple IP vendors and internal teams.