Senior SoC Interconnect Architect & Team Lead

Arm

Austin (TX)

Hybrid

USD 242,760 - 314,160

Full time

14 days+
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Job summary

Arm is seeking an experienced SoC Interconnect Technology Team Lead to drive architecture, design, and execution of next-generation coherent and non-coherent interconnect solutions for advanced SoCs.

You will lead a high-performing team delivering robust interconnect IP and shaping future SoC architectures, collaborating with CPU, GPU, NPU, memory, and system teams to ensure performance and power efficiency.

Qualifications

  • 15+ years of SoC architecture/design experience focusing on interconnects.
  • Proven track record delivering large-scale mobile or compute SoCs.
  • Deep knowledge of coherent interconnect protocols (AMBA ACE/CHI, CCIX, CXL).
  • Experience with non-coherent interconnects (AXI, NoC).
  • Strong performance, power, and system-level optimization skills.

Responsibilities

  • Lead architecture and development of coherent and non-coherent interconnect fabrics for complex SoCs.
  • Define system-level interconnect strategies including QoS, latency, bandwidth, and power.
  • Collaborate with CPU, GPU, memory, and system teams for integration and scaling.
  • Drive adoption of industry standards (AMBA AXI/ACE/CHI).
  • Own performance modeling, bottleneck analysis, and trade-offs.
  • Guide microarchitecture, RTL design, and verification for interconnect IP.
  • Mentor a team of architects and engineers.
  • Contribute to roadmap planning for next-gen interconnect tech.

Skills

SoC Architecture
Interconnect IP
Leadership
Performance Modeling
System-level optimization
AMBA ACE CHI CXL

Job description

Arm is seeking an experienced SoC Interconnect Technology Team Lead to drive architecture, design, and execution of next-generation coherent and non-coherent interconnect solutions for advanced SoCs.

You will lead a high-performing team delivering robust interconnect IP and shaping future SoC architectures, collaborating with CPU, GPU, NPU, memory, and system teams to ensure performance and power efficiency.

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