SoC Engineer - AI Accelerator Bring-up

OpenAI, Inc.

San Francisco (CA)

On-site

USD 180,000 - 240,000

Full time

4 days ago
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Job summary

OpenAI, Inc. is seeking a SoC Engineer to architect, design, and integrate first‑party AI accelerators. You will build the processor, interconnect, I/O, and platform infrastructure that connects accelerator designs into complete, functional systems.

This role blends architectural judgment with hands‑on implementation, collaborating with design, verification, firmware, and software teams from subsystem definitions through pre‑silicon validation, silicon bring‑up, and post‑silicon debug.

Qualifications

  • Experience in SoC architecture, RTL design, and full‑chip integration.
  • Hands‑on ownership through implementation and silicon bring‑up.
  • Familiarity with Arm Cortex subsystems and AMBA interconnects (AXI/APB).
  • Experience with PCIe, high‑speed I/O, SerDes/PHY.
  • Experience coordinating with third‑party IP vendors to drive integration and debug.
  • Understanding reset/boot architecture and firmware/software interactions.

Responsibilities

  • Define and implement SoC architectures spanning embedded processors, AMBA interconnects, peripheral subsystems, PCIe, Ethernet, and die‑to‑die interfaces.

Skills

SoC architecture
RTL design
Subsystem integration
Arm Cortex-M
Arm Cortex-A
AXI/APB
PCIe
SerDes/PHY
Verilog/SystemVerilog
Scripting/automation
Debug and security
Firmware interfaces
Third‑party IP integration
Pre-silicon validation
Post-silicon bring-up

Tools

Arm AMBA interconnects

Job description

OpenAI, Inc. is seeking a SoC Engineer to architect, design, and integrate first‑party AI accelerators. You will build the processor, interconnect, I/O, and platform infrastructure that connects accelerator designs into complete, functional systems.

This role blends architectural judgment with hands‑on implementation, collaborating with design, verification, firmware, and software teams from subsystem definitions through pre‑silicon validation, silicon bring‑up, and post‑silicon debug.

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