SMTS Product Architect

1040 Micron Semiconductor Prds; Boise (ID); On-site; USD 177,000 - 387,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

Paid time-off program

Paid family leave

Job summary

1040 Micron Semiconductor Prds is hiring a CMBU Product Architecture Engineer for DRAM in Boise, Idaho. The role involves developing an understanding of DRAM technologies and guiding strategies for AI training and inference.

Key responsibilities include analyzing architectures, addressing system bottlenecks, and mentoring junior engineers. Candidates need a Bachelor's in Electrical Engineering and 12+ years of experience in the field, along with familiarity with related technologies.

The position offers a base salary of USD $177,000.00 to $387,000.00, along with comprehensive medical benefits and paid time off.

Qualifications

• 12+ years of engineering experience.
• Familiarity with LPDDR and/or DRAM module architectures.
• Understanding of memory hierarchy, controllers, PHY, and custom SoC/ASIC design.

Responsibilities

• Explore and analyze system architectures using modeling, simulation, and prototyping tools.
• Identify system bottlenecks with customers and partners and propose innovative solutions.
• Lead path‑finding efforts for architectures using LPDDR and DRAM module technologies.

Skills

Modeling and simulation tools

Identifying system bottlenecks

Mentoring junior architects

Education

Bachelor’s degree in Electrical Engineering

Tools

TSV technologies

3D packaging technologies

Job description

Micron Technology is seeking a CMBU Product Architecture Engineer for DRAM. In this role you will develop a deep understanding of Micron’s DRAM technologies and market trends, and will help guide Micron’s DRAM strategy for AI training and inference.

Responsibilities

• Explore and analyze system architectures using modeling, simulation, and prototyping tools.
• Identify system bottlenecks with customers and partners and propose innovative solutions.
• Lead path‑finding efforts for architectures using LPDDR and DRAM module technologies.
• Define memory features that increase DRAM value in AI workloads.
• Mentor junior system architects and engineers.

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering.
• 12+ years of engineering experience.
• Familiarity with LPDDR and/or DRAM module architectures.
• Understanding of memory hierarchy, controllers, PHY, and custom SoC/ASIC design.
• Experience with TSV, stacked packaging, or 3D packaging technologies.

Preferred Qualifications

• Knowledge of memory subsystems in high‑performance computing.
• Exposure to HW/SW co‑optimization or regenerative AI frameworks.
• Experience participating in JEDEC or other specification‑setting activities.

Salary & Benefits

USD $177,000.00‑$387,000.00 base salary (US only). Compensation may include bonuses and equity.

• Medical, dental, and vision plans available.
• Paid time‑off program and paid holidays.
• Paid family leave.
• Robust benefit programs to protect income when unable to work due to illness or injury.

Micron is an equal‑opportunity workplace and an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity, or other characteristics protected by law.