Silicon Validation Engineer 3: SoC, PCIe & Debug (Onsite)

Experis Technology Group; Hillsboro (OR); On-site; USD 83,000 - 88,000; Full time

Benefits offered by this job

Medical Plan

Prescription Drug Plan

Dental Plan

Vision Plan

Health Savings Account

Health Spending Account

Dependent Care FSA

Life Insurance

Disability Insurance

Business Travel Insurance

401(k) Match

Weekly Pay

Job summary

Experis Technology Group is seeking a Silicon Validation Engineer 3 in Hillsboro, OR, onsite in a lab environment. You will run and maintain silicon system regressions and execute validation plans for SoC features across functional, electrical, and power/performance areas.

The role requires 3+ years in silicon validation, experience with PCIe/CXL/IO, strong debugging skills with oscilloscopes and logic analyzers, and proficiency in Python or C/C++. Verilog knowledge is a plus.

Qualifications

• 3+ years of hands-on silicon validation or debugging experience.
• Validation experience in PCIe, CXL, IO, endpoints, power management, BIOS/FW is a plus.
• Knowledge of high-speed IO interfaces and system-level validation principles.
• Proficiency in Python or C/C++ with some Verilog knowledge.

Responsibilities

• Run, triage, and maintain silicon system regressions for validation coverage.
• Execute validation test plans for SoC features across functional, electrical, and power/performance areas.
• Report results with clear summaries of outcomes, risks, and next steps.
• Analyze test results to identify, isolate, and debug issues using debugging tools.
• Review and validate system updates to confirm expected behavior and performance.

Skills

PCIe

CXL

IO

Python

C/C++

Verilog

Tools

Oscilloscopes

Logic Analyzers

JTAG

BERT

Job description

Experis Technology Group is seeking a Silicon Validation Engineer 3 in Hillsboro, OR, onsite in a lab environment. You will run and maintain silicon system regressions and execute validation plans for SoC features across functional, electrical, and power/performance areas.

The role requires 3+ years in silicon validation, experience with PCIe/CXL/IO, strong debugging skills with oscilloscopes and logic analyzers, and proficiency in Python or C/C++. Verilog knowledge is a plus.